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參數(shù)資料
| 型號(hào)： | HEF4724BT |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | 8-bit addressable latch |
| 中文描述： | 4000/14000/40000 SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDSO16 |
| 封裝： | PLASTIC, SOT109-1, SO-16 |
| 文件頁(yè)數(shù)： | 2/7頁(yè) |
| 文件大?。?/td> | 71K |
| 代理商： | HEF4724BT |
January 1995
2
Philips Semiconductors
Product specification
8-bit addressable latch
HEF4724B
MSI
DESCRIPTION
The HEF4724B is an 8-bit addressable latch with three
address inputs (A
0
to A
2
), a data input (D), an active LOW
enable input (E), an active HIGH clear input (CL), and eight
parallel latch outputs (O
0
to O
7
).
When E and CL are HIGH, all outputs (O
0
to O
7
) are LOW.
Eight-channel demultiplexing or active HIGH 1-of-8
decoding with output enable operation occurs when CL is
HIGH and E is LOW. When CL and E are LOW, the
selected output (O
0
to O
7
; determined by A
0
to A
2
) follows
D. When E goes HIGH, the contents of the latch are
stored. When operating in the addressable latch mode
(E = CL = LOW), changing more than one bit of A
0
to
A
2
could impose a transient wrong address. Therefore,
this should only be done while in the memory mode
(E = HIGH, CL = LOW).
Fig.1 Functional diagram.
PINNING
FAMILY DATA, I
DD
LIMITS category MSI
See Family Specifications
HEF4724BP(N):
16-lead DIL; plastic
(SOT38-1)
16-lead DIL; ceramic (cerdip)
(SOT74)
16-lead SO; plastic
(SOT109-1)
HEF4724BD(F):
HEF4724BT(D):
( ): Package Designator North America
A
0
to A
2
A
E
CL
O
0
to O
7
address inputs
data input
enable input (active LOW)
clear input (active HIGH)
parallel latch outputs
Fig.2 Pinning diagram.
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