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參數(shù)資料
| 型號(hào)： | HEF4720BT |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | SRAM |
| 英文描述： | 256-bit, 1-bit per word random access memories |
| 中文描述： | 256 X 1 STANDARD SRAM, 580 ns, PDSO16 |
| 封裝： | PLASTIC, SO-16 |
| 文件頁(yè)數(shù)： | 13/16頁(yè) |
| 文件大?。?/td> | 180K |
| 代理商： | HEF4720BT |
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January 1995
13
Philips Semiconductors
Product specification
256-bit, 1-bit per word random access memories
HEF4720B
HEF4720V
Memory retention
It is sometimes necessary to ensure that the information
stored in the memory cannot be erased inadvertently. This
can be arranged by adding detection circuits, by measures
in the timing, and by the addition of a battery. With the
HEF4720B; V, memory retention is very easily obtained
because its current drain in the stand-by condition is
almost zero. The wide supply voltage range makes it
possible to keep the memory active by means of a simple
battery, thereby preventing information loss.
In designing the memory retention circuits, two aspects
should be kept in mind. The memory retention will not
function in an optimum way if the battery voltage is low or
if the voltage transitions at the address input are too slow.
The first of these is usually the result of using too simple a
battery back-up circuit, e.g. a battery charged via a diode
from the TTL supply voltage. In this case, the LOCMOS
supply voltage falls below the safe operating voltage.
Special arrangements should be made to overcome this.
Slow address transitions (the second cause of memory
loss) are due to a long RC-time in the power system. When
the power is switched on or off, the 5 V line changes
between 0 and 5 V in milliseconds to seconds so
producing a correspondingly long transition time in the
various logic outputs. This creates problems in the proper
operation of the HEF4720B; V, with loss of memory as a
possible result. This can be prevented by ensuring that
input rise and fall times do not exceed 10
μ
s.
Three possibilities for controlling the rise and fall times at
the HEF4720B; V interface are given here:
1.
LOCMOS gates can be connected between the
address latch and the HEF4720B; V (Fig.9). In the
event of a low voltage, or mains supply failure, the
gates can be blocked by a signal from the memory
retention logic thus isolating the HEF4720B; V from
the address and CS inputs.
2.
The interface power supply can be separated from the
TTL power supply by means of a low-value resistor
(Fig.10); a thyristor is connected from the interface
power supply to earth. The system is arranged so that,
upon switching off or failure of the interface supply, the
thyristor turns on thus ensuring a rapid fall of the
supply voltage.
3.
The best solution is to select the interface circuits from
the LOCMOS family and to feed all these circuits from
the battery (Fig.11). These stages then remain active
when the TTL 5 V supply fails. The interface circuits
are mostly only active on a clock pulse, have the
possibility of being inactive on a gate level, or can be
forced into one position.
相關(guān)PDF資料 |
PDF描述 |
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| HEF4720 | 256-bit, 1-bit per word random access memories |
| HEF4724BD | 8-bit addressable latch |
| HEF4724BF | 8-bit addressable latch |
| HEF4724BN | 8-bit addressable latch |
| HEF4724BP | 8-bit addressable latch |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HEF4750VD,112 | 制造商:NXP Semiconductors 功能描述:FREQUENCY SYNTHESIZER - Rail/Tube |
| HEF4794BP | 制造商:NXP Semiconductors 功能描述:Shift Register Single 8-Bit Serial to Serial/Parallel 16-Pin PDIP Tube |
| HEF4794BP,112 | 功能描述:LED照明驅(qū)動(dòng)器 8STG SHIFT/STORE REG W/LED DRIVER RoHS:否 制造商:STMicroelectronics 輸入電壓:11.5 V to 23 V 工作頻率: 最大電源電流:1.7 mA 輸出電流: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SO-16N |
| HEF4794BT | 制造商:NXP Semiconductors 功能描述:Shift Register Single 8-Bit Serial to Serial/Parallel 16-Pin SO Tube |
| HEF4794BT,112 | 功能描述:LED照明驅(qū)動(dòng)器 SHIFT/REGISTER STORE RoHS:否 制造商:STMicroelectronics 輸入電壓:11.5 V to 23 V 工作頻率: 最大電源電流:1.7 mA 輸出電流: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SO-16N |
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