
KING BILLION ELECTRONICS CO., LTD
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億
電
子
股
份
有
限
公
司
HE84G761
HE80004 Series
June 30, 2003
This specification is subject to change without notice. Please contact sales person for the latest version before use.
5
V1.01
Pin Name
LGS2
LVP
LCAP4A
LCAP2B
LCAP2A
LCAP1A
LCAP1B
LCAP3A
Pin # I/O
40
41
42
43
44
45
46
47
Description
I
P Charge Pump Output.
O Charge Pump Capacitor Pin.
O Charge Pump Capacitor Pin.
O Charge Pump Capacitor Pin.
O Charge Pump Capacitor Pin.
O Charge Pump Capacitor Pin.
O Charge Pump Capacitor Pin.
Voltage Regulator Output. VDD is regulated to generate LVREG, which is in turns
pumped to LVP. Adjust resistor between LGS1 and LVREG to set LVREG voltage.
I
Regulator Voltage Setting
O Reference Voltage Output. Fixed 0.9 Volt DC reference voltage
O LCD frame signal for interfacing with LCD segment extender KDGS80.
O LCD data load pin for interfacing with LCD segment extender KDGS80.
P Power ground Input.
O Output of OP Amp.
I
Non-inverting input of OP Amp.
I
Inverting input of OP Amp.
O Alternate output of DAC.
O DAC Output.
System Reset input pin. Level trigger, active low on this pin will put the chip in reset
state.
External fast clock pin. Two types of oscillator can be selected by MO_FXTAL (‘0’ for
RC type and ‘1’ for crystal type). For RC type oscillator, one resistor needs to be
connected between FXI and GND. For crystal oscillator, one crystal needs to be placed
between FXI and FXO. Please refer to application circuit for details.
Test input pin. Please bond this pad and reserve a test point on PCB for debugging. But
for improving ESD, please connect this point with zero Ohm resistor to GND.
External slow clock pins. Slow clock is clock source for LCD display, TIMER1,
Time-Base and other internal blocks. Both crystal and RC oscillator are provided. The
slow clock type can be selected by mask option MO_SXTAL. Choose ‘0’ for RC type
and ‘1’ for crystal oscillator.
Input pin for x32 PLL circuit. Connect to external resistor and capacitors as shown in
application circuit.
Positive power Input. A 0.1 μF decoupling capacitors should be placed as close to IC
VDD and GND pads as possible for best decoupling effect.
8-bit bi-directional I/O port 10. The output type of I/O pad can also be selected by mask
option MO_10PP[7..0] (‘1’ for push-pull and ‘0’ for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using the I/O
pad as input pad, “1” must be outputted before reading.
8-bit bi-directional I/O port D. The output type of I/O pad can also be selected by mask
option MO_DPP[7..0] (‘1’ for push-pull and ‘0’ for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using the I/O as
input, ‘1’ must be outputted before reading the pin.
PRTD[7..2] can be used as wake-up pins. PRTD[7..6] can be as external interrupt
sources.
PRTD[1] shares pad with UART Receiver SIN pin.
PRTD[0] shares pad with UART transmitter SOUT pin.
8-bit bi-directional I/O port C. The output type of I/O pad can also be selected by mask
option MO_CPP[7..0] (‘1’ for push-pull and ‘0’ for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using the I/O as
input, ‘1’ must be outputted before reading the pin.
P Dedicated power input for RAM
O The Infrared output.
The PWM output can drive speaker or buzzer directly. Using VDD & PWM to drive
output device.
P Dedicated Ground for PWM output.
LCD Drive Voltage Setting
LVREG
48
O
LGS1
LVAG
OLFR
OCCK
GND
OPO
OPIP
OPIN
DAO
VO
49
50
51
52
53
54
55
56
57
58
RSTP_N
59
I
FXO,
FXI
60,
61
O,
B
TSTP_P
62
I
SXO,
SXI
63,
64
O,
I
VX
65
I
VDD
66
P
PRT10[7..0]
67~74 B
PRTD[7..2]
PRTD[1]/SIN
PRTD[0]/SOUT
75~82 B
PRTC[7:0]
83~90 B
VDD_RAM
IRO
91
92
PWM
93
O
GND_PWM
94