參數(shù)資料
型號: HD74SSTV16857
廠商: Hitachi,Ltd.
英文描述: 1:1 14-bit SSTL_2 Registered Buffer(1:1 14-位 SSTL_2 寄存緩沖器)
中文描述: 1:1 14位SSTL_2注冊緩沖區(qū)(1:1 14 -位SSTL_2寄存緩沖器)
文件頁數(shù): 1/15頁
文件大小: 64K
代理商: HD74SSTV16857
HD74SSTV16857
1:1 14-bit SSTL_2 Registered Buffer
ADE-205-336E (Z)
6th. Edition
May 2000
Description
The HD74SSTV16857 is a 14-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and
LVCMOS reset (
RESET
) input / SSTL_2 data (D) inputs and CLK input.
Data flow from D to Q is controlled by differential clock pins (CLK,
CLK
) and the
RESET
. Data is
triggered on the positive edge of the positive clock (CLK), and the negative clock (
CLK
) must be used to
maintain noise margins. When
RESET
is low, all registers are reset and all outputs are low.
To ensure defined outputs from the register before a stable clock has been supplied,
RESET
must be held in
the low state during power up.
Features
Supports LVCMOS reset (
RESET
) input / SSTL_2 data (D) inputs and CLK input
Differential SSTL_2 (Stub series terminated logic) CLK signal
Flow through architecture optimizes PCB layout
相關(guān)PDF資料
PDF描述
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