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參數(shù)資料
| 型號(hào)： | HD74HC589 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Triple 3-Input Positive-NOR Gates 14-CDIP -55 to 125 |
| 中文描述： | 8位Parallel-input/Serial-output串行移位寄存器（3態(tài)輸出） |
| 文件頁(yè)數(shù)： | 5/10頁(yè) |
| 文件大小： | 55K |
| 代理商： | HD74HC589 |
HD74HC589
5
AC Characteristics
(C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Ta = 25
°
C
Ta = –40 to
+85
°
C
Item
Symbol
V
CC
(V)
2.0
Min Typ Max Min
Max
Unit
Test Conditions
Maximum clock
f
max
—
—
5
—
4
MHz
frequency
4.5
—
—
27
—
21
6.0
—
—
32
—
25
Propagation delay t
PLH
time
2.0
—
—
200 —
250
ns
Latch clock to Q
H
t
PHL
4.5
—
20
40
—
50
6.0
—
—
34
—
43
t
PLH
t
PHL
2.0
—
—
175 —
220
ns
Shift clock to Q
H
4.5
—
15
35
—
44
6.0
—
—
30
—
37
t
PLH
t
PHL
2.0
—
—
175 —
220
ns
Serial shift/prallel load to Q
H
4.5
—
16
35
—
44
6.0
—
—
30
—
37
Output enable
t
ZL
t
ZH
2.0
—
—
150 —
190
ns
time
4.5
—
9
30
—
38
6.0
—
—
26
—
33
Output disable
t
LZ
t
HZ
2.0
—
—
150 —
190
ns
time
4.5
—
14
30
—
38
6.0
—
—
26
—
33
Pulse width
t
w
2.0
80
—
—
100
—
ns
4.5
16
8
—
20
—
6.0
14
—
—
17
—
Setup time
t
su
2.0
100 —
—
125
—
ns
Data to latch clock
4.5
20
1
—
25
—
6.0
17
—
—
21
—
t
su
2.0
100 —
—
125
—
ns
S
A
to shift clock
4.5
20
—
—
25
—
6.0
17
—
—
21
—
t
su
2.0
100 —
—
125
—
ns
Serial shift/parallel load to
4.5
20
—
—
25
—
shift clock
6.0
17
—
—
21
—
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