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參數(shù)資料
| 型號： | HD74HC597 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 8-bit Latch/Shift Register |
| 中文描述： | 8位鎖存器/移位寄存器 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大小： | 57K |
| 代理商： | HD74HC597 |
HD74HC597
8-bit Latch/Shift Register
Description
The HD74HC597 consists of an 8-bit storage latch feeding a parallel-in, serial-out 8-bit shift register. Both
the storage register and shift register have positive-edge triggered clocks. The shift register also has direct
load (from storage) and clear inputs.
Features
High Speed Operation: t
pd
(SCK to Q
H
’) = 14 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: V
CC
= 2 to 6 V
Low Input Current: 1 μA max
Low Quiescent Supply Current: I
CC
(static) = 4 μA max (Ta = 25°C)
Function Table
RCK
SCK
SLoad
SCLR
Function
X
X
X
Data loaded to input latches
X
L
H
Data loaded from inputs to shift register
X
X
L
H
Data transferred from input latches to shift register
X
X
L
L
Invalid logic, state of shift register indeterminate when signals
removed
X
X
H
L
Shift register cleared
X
H
H
Shift register clocked Q
n
= Q
n – 1
, Q
A
= SER
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