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參數(shù)資料
| 型號(hào)： | HD74HC279 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Octal Bus Transceivers With 3-State Outputs 20-CDIP -55 to 125 |
| 中文描述： | 四。簡(jiǎn)鎖存 |
| 文件頁(yè)數(shù)： | 1/9頁(yè) |
| 文件大?。?/td> | 59K |
| 代理商： | HD74HC279 |
HD74HC279
Quad.
S
–
R
Latches
Description
The latch is ideally suited for use as temporary stage for binary information processing and input/output
units. When either
S
or
R
is low, output is dependent on
R
input. When both inputs are high, Output is
stored before the indicated steady-state input conditions were established. And when both inputs are low,
output is high, but this high level are uncontinuance, if either of input goes high.
Features
High Speed Operation: t
pd
(
S
to Q) = 10 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: V
CC
= 2 to 6 V
Low Input Current: 1 μA max
Low Quiescent Supply Current: I
CC
(static) = 2 μA max (Ta = 25°C)
Function Table
Input
S
*
2
Output
R
Q
H
H
Q
0
H
L
H
H
L
L
L
H :
L
Q
0
:
Notes: 1. It is unpredictable, if
S
or
R
goes High.
2. As to latches which has two
S
inputs.
H: Both of
S
inputs are high.
L: Either or both of
S
inputs are low.
L
H*
1
High level
Low level
The level of Q respectively, before the indicated steady-state input conditions were established.
:
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