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參數(shù)資料
| 型號(hào)： | HD74HC294 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Programmable Frequency Divider/Digital Timer |
| 中文描述： | 可編程分頻器/數(shù)字定時(shí)器 |
| 文件頁(yè)數(shù)： | 1/12頁(yè) |
| 文件大?。?/td> | 68K |
| 代理商： | HD74HC294 |
HD74HC292/HD74HC294
Programmable Frequency Divider/Digital Timer
Description
This device divides the incoming clock frequency by a number (a power of 2) that is preset by the
Programming inputs. It has two Clock inputs, either of which may be used as a clock inhibit. The device
also has an active-low Reset, which initializes the internal flip-flop states. Test Point outputs (TP1, TP2,
TP3) are provided with HD74HC292 to facilitate incoming inspections.
Test Point output is provided with HD74HC294 to facilitate incoming inspections.
Features
High Speed Operation: t
pd
(Clock to Q) = 16 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: V
CC
= 2 to 6 V
Low Input Current: 1 μA max
Low Quiescent Supply Current: I
CC
(static) = 4 μA max (Ta = 25°C)
Function Table
CLR
CLK1
CLK2
Q Output Mode
L
X
X
Cleared to L
H
L
Count
H
L
Count
H
H
X
Inhibit
H
X
H
Inhibit
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