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參數(shù)資料
| 型號(hào)： | HD74HC166 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Octal Buffers/Drivers With 3-State Outputs 20-CDIP -55 to 125 |
| 中文描述： | 并聯(lián)負(fù)載8位的移位寄存器 |
| 文件頁(yè)數(shù)： | 1/10頁(yè) |
| 文件大?。?/td> | 57K |
| 代理商： | HD74HC166 |
HD74HC166
Parallel-load 8-bit Shift Register
Description
This device is an 8-bit shift register with an output from the last stage. Data may be loaded into the register
either in parallel or in serial form. When the Shift/Load input is low, the data is loaded asynchronously in
parallel. When the Shift/Load input is high, the data is loaded serially on the rising edge of either clock
inhibit or Clock. Clear is asynchronous and active-low.
The 2-input NOR clock may be used either by combining two independent clock sources or by designating
one of the clock inputs to act as a clock inhibit.
Features
High Speed Operation: t
pd
(Clock to Q
H
) = 14 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: V
CC
= 2 to 6 V
Low Input Current: 1 μA max
Low Quiescent Supply Current: I
CC
(static) = 4 μA max (Ta = 25°C)
Function Table
Inputs
Parallel
Internal Outputs
Output
Clear
Shift/Load
Clock Inhibit
Clock
Serial
A ··· H
Q
A
L
Q
B
L
Q
H
L
L
X
X
X
X
X
H
X
L
L
X
X
Q
A0
a
Q
B0
b
Q
H0
h
H
L
L
X
a ··· h
H
H
L
H
X
H
Q
An
Q
Gn
H
H
L
L
X
L
Q
An
Q
Gn
H
X
H
X
X
Q
A0
Q
B0
Q
H0
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