參數(shù)資料
型號： HD66841
廠商： Hitachi,Ltd.
英文描述： LVIC-II (LCD Video Interface Controller)(LCD視頻控制器)
中文描述： LVIC - 2（液晶視頻接口控制器）（液晶顯示視頻控制器）
文件頁數(shù)： 7/62頁
文件大小： 185K
代理商： HD66841
HD66841
7
Buffer Memory Interface
MCS0
,
MCS1
:
MCS0
and
MCS1
output the buffer memory chip select signal.
MWE
:
MWE
outputs the write enable signal of buffer memories.
MA0–MA15:
MA0–MA15 output buffer memory addresses.
RD0–RD7:
RD0–RD7 transfer data between R data buffer memory and the LVIC.
GD0–GD7:
GD0–GD7 transfer data between G data buffer memory and the LVIC.
BD0–BD7:
BD0–BD7 transfer data between B data buffer memory and the LVIC.
Mode Setting
PMOD0, PMOD1:
The PMOD0–PMOD1 input signals select a programming method (Table 6).
DOTE:
The DOTE input signal switches the timing of the data latch. The LVIC latches R, G and B signal
at the falling edge of DOTCLK when DOTE is high, and at the rising edge when low.
SPS:
The SPS input signal selects the polarity of VSYNC. (The polarity of HSYNC is fixed.) VSYNC is
high active when SPS is high, and low active when low.
DM0–DM3:
The DM0–DM3 input signals select a display mode (Table 8).
MS0–MS1:
The MS0–MS1 input signals select the kind of buffer memories (Table 2).
XDOT:
The XDOT input signal specifies the number of horizontal displayed characters. The number is 90
when XDOT is high, and 80 when low.
YL0–YL2:
The YL0–YL2 input signals specify the number of vertical displayed lines (Table 3).
ADJ:
The ADJ input signal determines whether F0–F3 pins adjust the number of vertical displayed lines or
the display timing signal. F0–F3 pins adjust the display timing signal when ADJ is high, and adjust the
number of vertical displayed lines when low.
F0–F3:
F0–F3 input data for adjusting the number of vertical displayed lines (Table 4), or the display
timing signal (see “Fine Adjustment of Display Timing Signal”).
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