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參數(shù)資料
| 型號： | HD66503 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 240-Channel Common Driver with Internal LCD Timing Circuit(帶內(nèi)部LCD定時電路的240通道驅(qū)動器) |
| 中文描述： | 240頻道共同的內(nèi)部LCD定時電路（帶內(nèi)部液晶定時電路的240通道驅(qū)動器驅(qū)動程序） |
| 文件頁數(shù)： | 23/28頁 |
| 文件大?。?/td> | 107K |
| 代理商： | HD66503 |
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HD66503
23
Item
Symbol
Min
Typ
Max
Unit
Measurement
Condition
Notes
Power
consumption
I
EE
—
—
20
μ
A
Master mode
1/240 duty cycle,
C
f
= 100 pF,
R
f
= 180 k
V
CC
–GND = 3V
V
CC
–V
EE
= 28V,
7, 11
Notes: 1. Applies to input pins MEOR, MWS0 to MWS5, DUTY, SHL,
DISPOFF
, M/
S
,
RESET
, and CR,
and when inputting to input/output pins CL1, FLM,
DOC
, and M.
2. Applies when outputting from input/output pins CL1, FLM,
DOC
, and M.
3. Applies to V1L/R, V2L/R, V5L/R, and V6L/R. X1 to X240 are open.
4. Figure 17 shows the external clock specifications:
TH
0.8V
CC
0.5V
CC
0.2V
CC
t
rcp
t
fcp
TL
CR
OPEN
R
C
External
clock
OPEN
Min
45
—
—
Typ
50
—
—
Max
55
50
50
Unit
%
ns
ns
Duty
t
rcp
t
fcp
TH
TH + TL
Duty =
×
100%
Figure 17 External Clock
5. Regulates to operation frequency limits of the bidirectional shift register in the slavemode.
6. Connect resistance Rf and capacitance Cf as follows:
CR
C
f
R
f
R
C
Figure 18 Timing Components
7. Input and output currents are excluded. When a CMOS input is floating, excess current flows
from the power supply through to the input circuit. To avoid this, VIH and VIL must be held to V
CC
and GND levels, respectively.
8. This value is specified for the current flowing through GND under the following conditions:
Internal oscillation circuit is used. Each terminal of MEOR, MWS0 to MWS5, DUTY, SHL,
DISPOFF
, M/
S
, and
RESET
is connected to V
CC
. Oscillator is set as described in note 6.
9. This value is specified for the current flowing through GND under the following conditions: Each
terminal of MEOR, MWS0 to MWS5, DUTY, SHL,
DISPOFF
, M/
S
, and
RESET
is connected to
V
CC
. Oscillator is set as described in note 4.
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