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參數(shù)資料
| 型號： | HD66503 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 240-Channel Common Driver with Internal LCD Timing Circuit(帶內(nèi)部LCD定時(shí)電路的240通道驅(qū)動(dòng)器) |
| 中文描述： | 240頻道共同的內(nèi)部LCD定時(shí)電路（帶內(nèi)部液晶定時(shí)電路的240通道驅(qū)動(dòng)器驅(qū)動(dòng)程序） |
| 文件頁數(shù)： | 11/28頁 |
| 文件大小： | 107K |
| 代理商： | HD66503 |
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HD66503
11
Internal Function Description
1. Generation of Signals CL1 and FLM:
Signal CL1 shifts the scanning signal of the common driver. It
is a 50% duty-ratio clock that changes level synchronously with the rising edge of oscillator clock CR.
FLM is a clock signal that is output once every 240 CL1 clock cycles for a duty of 1/240 (DUTY = V
CC
),
and every 120 CL1 clock cycles for a duty of 1/120 (DUTY = GND).
2. Generation of Signal M:
Signal M alternates current in the LCD. It alternates the current to decrease
cross talk after a certain number of lines ranging from 2 to 63 lines. The number of lines can be specified
with pins MWS0 to MWS5 by setting each pin to either V
CC
or GND (H or L). In addition, when pin
MEOR is connected to GND, signal M is a simple line alternating waveform, and when pin MEOR is
connected to V
CC
, signal M is an EOR (exclusive OR) of line alternating waveform and frame alternating
waveform.
1
2
240
(120)
CR
CL1
FLM
Figure 6 Generation of Signals CL1 and FLM
(When MWS0 to MWS5 = 6)
M
(MEOR = GND)
M
(MEOR = V
CC
)
1
2
3
4
5
6
1
2
FLM
CL1
Figure 7 Generation of Signal M
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