
vii
Section 10 14-Bit PWM D/A..........................................................................251
10.1 Overview ....................................................................................................................... 251
10.1.1 Features ............................................................................................................ 251
10.1.2 Block Diagram.................................................................................................. 252
10.1.3 Pin Configuration.............................................................................................. 252
10.1.4 Register Configuration ...................................................................................... 253
10.2 Register Descriptions ..................................................................................................... 254
10.2.1 PWM D/A Counter (DACNT)........................................................................... 254
10.2.2 D/A Data Registers A and B (DADRA and DADRB)........................................ 255
10.2.3 PWM D/A Control Register (DACR) ................................................................ 257
10.2.4 Module Stop Control Register (MSTPCR) ........................................................ 259
10.3 Bus Master Interface ...................................................................................................... 260
10.4 Operation ....................................................................................................................... 263
Section 11 16-Bit Free-Running Timer...........................................................267
11.1 Overview ....................................................................................................................... 267
11.1.1 Features ............................................................................................................ 267
11.1.2 Block Diagram.................................................................................................. 268
11.1.3 Input and Output Pins ....................................................................................... 269
11.1.4 Register Configuration ...................................................................................... 270
11.2 Register Descriptions ..................................................................................................... 271
11.2.1 Free-Running Counter (FRC) ............................................................................ 271
11.2.2 Output Compare Registers A and B (OCRA, OCRB) ........................................ 272
11.2.3 Input Capture Registers A to D (ICRA to ICRD)............................................... 273
11.2.4 Output Compare Registers AR and AF (OCRAR, OCRAF) .............................. 274
11.2.5 Output Compare Register DM (OCRDM) ......................................................... 275
11.2.6 Timer Interrupt Enable Register (TIER)............................................................ 275
11.2.7 Timer Control/Status Register (TCSR).............................................................. 278
11.2.8 Timer Control Register (TCR) .......................................................................... 282
11.2.9 Timer Output Compare Control Register (TOCR)............................................. 284
11.2.10 Module Stop Control Register (MSTPCR) ...................................................... 286
11.3 Operation ....................................................................................................................... 287
11.3.1 FRC Increment Timing ..................................................................................... 287
11.3.2 Output Compare Output Timing........................................................................ 288
11.3.3 FRC Clear Timing ............................................................................................ 289
11.3.4 Input Capture Input Timing............................................................................... 289
11.3.5 Timing of Input Capture Flag (ICF) Setting ...................................................... 291
11.3.6 Setting of Output Compare Flags A and B (OCFA, OCFB)............................... 292
11.3.7 Setting of FRC Overflow Flag (OVF) ............................................................... 293
11.3.8 Automatic Addition of OCRA and OCRAR/OCRAF ........................................ 294
11.3.9 ICRD and OCRDM Mask Signal Generation .................................................... 295
11.4 Interrupts........................................................................................................................ 296