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23.5.2
Usage Note
If there is conflict between DTC module stop mode setting and a DTC bus request, the bus
request has priority and the MSTP bit will not be set to 1.
Write 1 to the MSTP bit again after the DTC bus cycle.
When using an H8S/2134 Series MCU, the MSTP bits for nonexistent modules must not be set
to 1.
23.6
Software Standby Mode
23.6.1
Software Standby Mode
If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, the LSON bit in
LPWRCR is cleared to 0, and the PSS bit in TCSR (WDT1) is cleared to 0, software standby
mode is entered. In this mode, the CPU, on-chip supporting modules, and oscillator all stop.
However, the contents of the CPU’s internal registers, RAM data, and the states of on-chip
supporting modules other than the SCI, PWM, and PWMX, and of the I/O ports, are retained.
In this mode the oscillator stops, and therefore power dissipation is significantly reduced.
23.6.2
Clearing Software Standby Mode
Software standby mode is cleared by an external interrupt (NMI pin, or pin
,54, ,54, ,54,
,54, or ,54), or by means of the 5(6 pin or 67%< pin.
Clearing with an Interrupt: When an NMI, IRQ0, IRQ1, IRQ2, IRQ6, or IRQ7 interrupt
request signal is input, clock oscillation starts, and after the elapse of the time set in bits STS2 to
STS0 in SYSCR, stable clocks are supplied to the entire chip, software standby mode is cleared,
and interrupt exception handling is started.
Software standby mode cannot be cleared with an IRQ0, IRQ1, IRQ2, IRQ6, or IRQ7 interrupt if
the corresponding enable bit has been cleared to 0 or has been masked by the CPU.
Clearing with the
5(6
5(6 Pin: When the 5(6 pin is driven low, clock oscillation is started. At the
same time as clock oscillation starts, clocks are supplied to the entire chip. Note that the
5(6
pin must be held low until clock oscillation stabilizes. When the
5(6 pin goes high, the CPU
begins reset exception handling.
Clearing with the
67%<
67%< Pin: When the 67%< pin is driven low, a transition is made to
hardware standby mode.