4.1.1
4.1.2
4.1.3
Reset..................................................................................................................................
4.2.1
Reset Types..........................................................................................................
4.2.2
Power-On Reset....................................................................................................
4.2.3
Manual Reset........................................................................................................
Address Errors...................................................................................................................
4.3.1
Address Error Sources..........................................................................................
4.3.2
Address Error Exception Processing....................................................................
Interrupts............................................................................................................................
4.4.1
Interrupt Sources..................................................................................................
4.4.2
Interrupt Priority Rankings...................................................................................
4.4.3
Interrupt Exception Processing ............................................................................
Instruction Exceptions.......................................................................................................
4.5.1
Types of Instruction Exceptions...........................................................................
4.5.2
Trap Instruction....................................................................................................
4.5.3
Illegal Slot Instruction..........................................................................................
4.5.4
General Illegal Instructions..................................................................................
Cases in Which Exceptions Are Not Accepted .................................................................
4.6.1
Immediately after Delayed Branch Instructions...................................................
4.6.2
Immediately after Interrupt-Disabling Instructions..............................................
Stack Status after Exception Processing............................................................................
Notes..................................................................................................................................
4.8.1
Value of the Stack Pointer (SP)............................................................................
4.8.2
Value of the Vector Base Register (VBR) ...........................................................
4.8.3
Address Errors that Are Caused by Stacking During Address Error
Exception Processing............................................................................................
Exception Processing Types and Priorities..........................................................
Exception Processing Operation ..........................................................................
Exception Process Vector Table ..........................................................................
47
49
49
51
51
51
52
52
52
53
54
54
54
55
55
55
55
56
56
57
57
57
58
59
59
59
4.2
4.3
4.4
4.5
4.6
4.7
4.8
59
Section 5 Interrupt Controller (INTC)
...........................................................................
5.1
Overview............................................................................................................................
5.1.1
Features ................................................................................................................
5.1.2
Block Diagram......................................................................................................
5.1.3
Pin Configuration .................................................................................................
5.1.4
Registers...............................................................................................................
5.2
Interrupt Sources................................................................................................................
5.2.1
NMI Interrupts......................................................................................................
5.2.2
User Break Interrupt.............................................................................................
5.2.3
IRQ Interrupts ......................................................................................................
5.2.4
On-Chip Interrupts................................................................................................
5.2.5
Interrupt Exception Vectors and Priority Rankings .............................................
5.3
Register Descriptions.........................................................................................................
5.3.1
Interrupt Priority Registers A–E (IPRA–IPRE)...................................................
61
61
61
61
63
63
63
64
64
64
64
65
68
68