116 HITACHI
Table 8.6
How Space is Divided
Area Address
0
H'0000000 – H'0FFFFFF
Assign-able Memory
On-chip ROM*
1
Capacity
(linear space)
16 kB*
3
32 kB*
4
4 MB
4 MB
16 MB
4 MB
4 MB
4 MB
512 B
4 MB
4 MB
4 MB
16 kB*
3
32 kB*
4
4 MB
4 MB
16 MB
4 MB
4 MB
4 MB
4 MB
4 MB
1 kB
Bus
Width
32
CS
Output
—
External memory*
2
External memory
DRAM*
6
External memory
External memory
External memory
On-chip peripheral module
External memory*
9
Multiplexed I/O
External memory
On-chip ROM*
1
8/16*
5
8
8
8
8
8
7
8/16*
8
CS0
CS1
RAS CAS
CS2
CS3
CS4
—
CS6
1
H'1000000 – H'1FFFFFF
2
3
4
5
6
H'2000000 – H'2FFFFFF
H'3000000 – H'3FFFFFF
H'4000000 – H'4FFFFFF
H'5000000 – H'5FFFFFF
H'6000000 – H'6FFFFFF
7
0
H'7000000 – H'7FFFFFF
H'8000000 – H'8FFFFFF
8
32
CS7
—
External memory*
2
External memory
DRAM*
6
8/16*
5
16
16
16
16
16
16
16
32
CS0
CS1
RAS CAS
CS2
CS3
CS4
CS5
CS6
—
1
H'9000000 – H'9FFFFFF
2
3
4
5
6
7
Notes: 1. When MD2–MD0 pins are 010
2. When MD2–MD0 pins are 000 or 001
3. For SH7020
4. For SH7021
5. Select with MD0 pin
6. Select with DRAME bit in BCR
7. Divided into 8-bit and 16-bit space according to value of address bit A8 (Long word
accesses are inhibited, however, in on-chip peripheral modules with bus widths of 8
bits. Some on-chip peripheral modules with bus widths of 16 bits also have registers
that are only byte-accessible and registers for which byte access is inhibited. For
details, see the sections on the individual modules.)
8. Divided into 8-bit space and 16-bit space by value of address bit A14
9. Select with IOE bit of BCR
H'A000000 – H'AFFFFFF External memory
H'B000000 – H'BFFFFFF External memory
H'C000000 – H'CFFFFFF External memory
H'D000000 – H'DFFFFFF External memory
H'E000000 – H'EFFFFFF External memory
H'F000000 – H'FFFFFFF On-chip RAM