
Table 6-4 Addresses of DTC Vectors (cont)
6.3.3 Location of Register Information in Memory
For each interrupt, the DTC control register information is stored in four consecutive words in
memory in the order shown in figure 6-5.
6.3.4 Length of Data Transfer Cycle
Table 6-5 lists the number of states required per data transfer, assuming that the DTC control
register information is stored in on-chip RAM. This is the number of states required for loading
and saving the DTC control registers and transferring one byte or word of data. Two cases are
considered: a transfer between on-chip RAM and a register belonging to an I/O port or on-chip
supporting module (i.e., a register in the register field from addresses H'FE80 to H'FFFF); and a
transfer between such a register and external RAM.
Address of DTC Vector
Minimum Mode
H'00F8 - H'00F9
H'00FA - H'00FB
H'00A2 - H'00A3
H'00A4 - H'00A5
H'00AA - H'00AB
H'00AC - H'00AD
H'00B0 - H'00B1
Interrupt
8-Bit
timer
SCI1
Maximum Mode
H'01F0 - H'01F3
H'01F4 - H'01F7
H'0144 - H'0147
H'0148 - H'014B
H'0154 - H'0157
H'0158 - H'015B
H'0160 - H'0163
CMIA
CMIB
RXI
TXI
RXI
TXI
ADI
SCI2
A/D converter
DTC vector table
Fig. 6-5
TA
TA + 2
RAM
DTMR
DTSR
DTDR
DTCR
8 Bits
8 Bits
TA + 4
TA + 6
Mode register
Source address register
Destination address register
Count register
Figure 6-5 Order of Register Information
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