5.6 Interrupt Response Time
Table 5-4 indicates the number of states that may elapse between the generation of an interrupt
request and the execution of the first instruction of the interrupt-handling routine, assuming that
the interrupt is not masked and not preempted by a higher-priority interrupt. Since word access is
performed to on-chip memory areas, fastest interrupt service can be obtained by placing the
program in on-chip ROM and the stack in on-chip RAM.
Table 5-4 Number of States before Interrupt Service
Note:
m: Number of wait states inserted in external memory access.
Values in parentheses are for the LDM instruction.
Number of States
No.
1
Reason for Wait
Interrupt priority decision and comparison with
mask level in CPU status register
Maximum number of
states to completion
of current instruction
Minimum Mode
2 states
Maximum Mode
2
Instruction is in on-chip
memory
x
(x = 38 for LDM instruction specifying
all registers)
y
(y = 74 + 16m for LDM instruction
specifying all registers)
16
28 + 6m
Instruction is in external
memory
3
Saving of PC and SR
or PC, CP, and SR
and instruction prefetch
Stack is in
on-chip RAM
Stack is in on-chip RAM
Stack is in external memory
21
41 + 10m
Instruction is in on-chip
memory
Instruction is in external
memory
Instruction is in on-chip
memory
Instruction is in external
memory
18 + x
(56)
18 + y
(92 + 16m)
30 + 6m + x
(68 + 6m)
30 + 6m + y
(104 + 22m)
23 + x
(61)
23 + y
(97 + 16m)
43 + 10m + x
(81 + 10m)
43 + 10m + y
(117 + 26m)
Total
Stack is in
external RAM
112