Section 18 Power-Down State
18.1 Overview
The H8/534 and H8/536 have a power-down state that greatly reduces power consumption by
stopping the CPU functions. The power-down state includes three modes:
1. Sleep mode—
a software-triggered mode in which the CPU halts but the rest of
the chip remains active
2. Software standby mode—
a software-triggered mode in which the entire chip is inactive
3. Hardware standby mode—
a hardware-triggered mode in which the entire chip is inactive
The sleep mode and software standby mode are entered from the program execution state by
executing the SLEEP instruction under the conditions given in table 18-1. The hardware standby
mode is entered from any other state by a Low input at the STBY pin.
Table 18-1 lists the conditions for entering and leaving the power-down modes. It also indicates
the status of the CPU, on-chip supporting modules, etc., in each power-down mode.
Table 18-1 Power-Down State
Entering
Procedure
Execute
SLEEP
instruction
Set SSBY bit
in SBYCR to
1, then
execute SLEEP
instruction
*
Set STBY
pin to Low
level
CPU
Reg’s.
Held
Sup.
Mod’s.
Run
I/O
Ports
Held
Exiting
Methods
Interrupt
RES Low
STBY Low
NMI
RES Low
STBY Low
Mode
Sleep
mode
Clock
Run
CPU
Halt
RAM
Held
Soft-
ware
standby
mode
Halt
Halt
Held
Halt
and
initialized
Held
Held
Hard-
ware
standby
mode
*
The watchdog timer must also be stopped.
Halt
Halt
Not
held
Halt
and
initialized
Held
High
impe-
dance
state
STBY High,
then RES
Low
→
High
Notes:
SBYCR Software standby control register
SSBY
Software standby bit
321