Rev. 4.00, 03/04, page xxv of xxviii
Tables
Section 1 Overview
Table 1.1
Pin Functions............................................................................................................8
Section 2 CPU
Table 2.1
Table 2.2
Table 2.3
Table 2.3
Table 2.4
Table 2.5
Table 2.6
Table 2.6
Table 2.7
Table 2.8
Table 2.9
Table 2.10
Table 2.11
Table 2.12
Table 2.12
Operation Notation .................................................................................................22
Data Transfer Instructions.......................................................................................23
Arithmetic Operations Instructions (1)...................................................................24
Arithmetic Operations Instructions (2)...................................................................25
Logic Operations Instructions.................................................................................26
Shift Instructions.....................................................................................................26
Bit Manipulation Instructions (1)............................................................................27
Bit Manipulation Instructions (2)............................................................................28
Branch Instructions.................................................................................................29
System Control Instructions....................................................................................30
Block Data Transfer Instructions............................................................................31
Addressing Modes ..................................................................................................33
Absolute Address Access Ranges...........................................................................34
Effective Address Calculation (1)...........................................................................36
Effective Address Calculation (2)...........................................................................37
Section 3 Exception Handling
Table 3.1
Exception Sources and Vector Address..................................................................47
Table 3.2
Interrupt Wait States...............................................................................................58
Section 4 Address Break
Table 4.1
Access and Data Bus Used .....................................................................................63
Section 5 Clock Pulse Generators
Table 5.1
Crystal Resonator Parameters.................................................................................69
Section 6 Power-Down Modes
Table 6.1
Operating Frequency and Waiting Time.................................................................75
Table 6.2
Transition Mode after SLEEP Instruction Execution and Interrupt Handling........79
Table 6.3
Internal State in Each Operating Mode...................................................................80
Section 7 ROM
Table 7.1
Table 7.2
Table 7.3
Setting Programming Modes ..................................................................................90
Boot Mode Operation .............................................................................................92
System Clock Frequencies for which Automatic Adjustment of
LSI Bit Rate is Possible..........................................................................................93
Reprogram Data Computation Table......................................................................96
Additional-Program Data Computation Table........................................................96
Programming Time.................................................................................................96
Table 7.4
Table 7.5
Table 7.6