13.1.2 Block Diagram...................................................................................................... 342
13.1.3 Input/Output Pins.................................................................................................. 343
13.1.4 Register Configuration ......................................................................................... 343
Register Descriptions......................................................................................................... 344
13.2.1 Receive Shift Register.......................................................................................... 344
13.2.2 Receive Data Register.......................................................................................... 344
13.2.3 Transmit Shift Register ........................................................................................ 344
13.2.4 Transmit Data Register......................................................................................... 345
13.2.5 Serial Mode Register............................................................................................ 345
13.2.6 Serial Control Register......................................................................................... 347
13.2.7 Serial Status Register............................................................................................ 351
13.2.8 Bit Rate Register (BRR)....................................................................................... 355
Operation ........................................................................................................................... 363
13.3.1 Overview.............................................................................................................. 363
13.3.2 Operation in Asynchronous Mode........................................................................ 366
13.3.3 Multiprocessor Communication........................................................................... 376
13.3.4 Clocked Synchronous Operation.......................................................................... 384
SCI Interrupt Sources and the DMAC............................................................................... 394
Usage Notes....................................................................................................................... 394
13.2
13.3
13.4
13.5
Section 14 Pin Function Controller (PFC)
.................................................................... 399
14.1
Overview............................................................................................................................ 399
14.2
Register Configuration ...................................................................................................... 401
14.3
Register Descriptions......................................................................................................... 401
14.3.1 Port A I/O Register (PAIOR)............................................................................... 401
14.3.2 Port A Control Registers (PACR1 and PACR2).................................................. 402
14.3.3 Port B I/O Register (PBIOR)................................................................................ 407
14.3.4 Port B Control Registers (PBCR1 and PBCR2)................................................... 408
14.3.5 Column Address Strobe Pin Control Register (CASCR)..................................... 413
Section 15 Parallel I/O Ports
............................................................................................. 415
15.1
Overview............................................................................................................................ 415
15.2
Port A................................................................................................................................. 415
15.2.1 Register Configuration ......................................................................................... 415
15.2.2 Port A Data Register (PADR).............................................................................. 416
15.3
Port B................................................................................................................................. 417
15.3.1 Register Configuration ......................................................................................... 417
15.3.2 Port B Data Register (PBDR)............................................................................... 418
Section 16 ROM
................................................................................................................... 419
16.1
Overview............................................................................................................................ 419
16.2
PROM Mode...................................................................................................................... 421
16.2.1 Setting the PROM Mode...................................................................................... 421