HD61602/HD61603
1234
Terminal Functions
HD61602 Terminal Functions
Terminal
Name
VDD
READY
No. of
Lines
1
1
Input/Output
Power supply
NMOS open
drain output
Connected to Function
Positive power supply.
While data is being set in the display data RAM
and mode setting latch in the LSI after data
transfer, low is output from the READY terminal
to inhibit the next data input.
There are two modes: one in which low is output
only when both of
&6
and
5(
are low, and the
other in which low is output regardless of
&6
and
5(
.
Chip select input. Data can be written only when
this terminal is low.
Write enable input. Input data of D0 to D7 is
latched at the rising edge of
:(
.
Resets the input data byte counter. After both
&6
and
5(
are low, the first data is recognized
as the 1st byte data.
High level input stops LSI operations.
1. Stops oscillation and clock input.
2. Stops LCD driver.
3. Stops writing data into display RAM.
Data input terminal for 8-bit
×
2-byte data.
Negative power supply.
Reference voltage output. Generates LCD
driving voltage.
Divides the reference voltage of VREF1 with
external R to determine LCD driving voltage.
VREF2
≈
V1.
Connection terminals for boosting C of LCD
driving voltage generator. An external C is
connected between VC1 and VC2.
LCD driving voltage outputs. An external C is
connected to each terminal.
LCD common (backplate) driving output.
LCD segment driving output.
Synchronous input for 2 or more chips
applications. LCD driver timing circuit is reset by
high input. LCD is off.
Attach external R to these terminals for
oscillation. An external clock (100 kHz) can be
input to OSC1.
MCU
&6
1
Input
MCU
:(
1
Input
MCU
5(
1
Input
MCU
SB
1
Input
MCU
D0–D7
VSS
VREF1
8
1
1
Input
Power supply
Output
MCU
External R
VREF2
1
Input
External R
VC1, VC2
2
Output
External C
V1, V2, V3
3
Output (Input)
External C
COM0–COM3 4
SEG0–SEG50 51
SYNC
Output
Output
Input
LCD
LCD
MCU
1
OSC1
OSC2
2
Input
Output
External R
Note: Logic polarity is positive. 1 = high = active.