參數(shù)資料
型號(hào)： HD49235
廠商： Hitachi,Ltd.
英文描述： 16 AMP SPDT MINIATURE POWER RELAY
中文描述： 數(shù)字信號(hào)處理器的CD
文件頁(yè)數(shù)： 25/41頁(yè)
文件大?。?/td> 192K
代理商： HD49235
HD49235FS
Rev.2, Aug. 1995, page 25 of 41
DWIDTH:
This bit selects the interval from the high-to-low transition of the defect detection signal
until termination of the digital PLL (and return to the analog PLL).
When DWIDTH = 0, termination occurs 8 frames past the fall of the defect detection signal if the defect
detection signal width was less than 12 frames, and 16 frames past the fall of the defect detection signal
if the defect detection signal width was 12 frames or more.
When DWIDTH = 1, termination occurs 4 frames past the fall of the defect detection signal if the defect
detection signal width was less than 12 frames, and 8 frames past the fall of the defect detection signal
if the defect detection signal width was 12 frames or more.
b. Function Selections (Register 9)
BI0 and BI1:
These bits select normal play, double-speed play, or quadruple-speed play.
Note:
When changing the playback speed, always switch the system to CLV stop mode so that the free-
running frequency is adjusted automatically. The period of setting is 30 msec or more.
WG10TL:
This bit selects the width of the frame synchronization signal (SYNC) detection window.
WG10TL = 0: The window width is ±10 T.
WG10TL = 1: The window width is ±19 T.
SYLCK0 and SYLCK1:
These bits select whether the sync protection state is maintained for 2, 4, 8, or
12 consecutive frames in which the frame synchronization signal (SYNC) is not detected.
CRCQ:
In Q code buffer mode (when the QDSEL signal at pin 65 is low), this bit selects whether or
not to insert the QOK flag into the Q code data.
c. Audio Control (Register A)
The audio control commands concerning the DAS output are all ignored in CD-ROM mode, which is
selected when the ROM microprocessor command bit is set to 1.
MUTEL and MUTER:
These command bits mute the left and right channels independently.
Attenuation is carried out in eight steps (7/8, 6/8, 5/8, 4/8, 3/8, 2/8, 1/8, 0) with 136 μs per step (at
standard speed).
Notes: 1. Muting begins as soon as the command is input, without waiting for a zero-crossing point.
2. If the external MUTE signal is high, both channels are muted regardless of these commands.
MONO:
This bit selects monaural audio output.
Note:
When MONO is set to 1, mean-value interpolation is not performed. The only type of interpolation
performed is to hold the preceding value.
ATT:
This bit attenuates the audio output level by –12 dB in six steps (7/8, 6/8, 5/8, 4/8, 3/8, 2/8).
Note:
If the external MUTE signal is high, both channels are muted regardless of this command bit.
BLGMAIN and BLGSUB:
These bits select whether or not to output bilingual audio on the left and
right channels. This command is ignored if “SWLR” = 1.
SOFTMT:
This command bit mutes both the left and right channels simultaneously. Attenuation is
carried out in eight steps with 136 μs per step (at standard speed).
Note:
If the external MUTE signal is high, both channels are muted regardless of this command bit.
SWLR:
Reverses the left- and right-channel outputs, by reversing DATA from RAM.
Note:
Clear this bit to 0 when using DAS subcode output.
相關(guān)PDF資料
PDF描述
HD49235FS Digital Signal Processor for CD
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HD49235FS 制造商:HITACHI 制造商全稱(chēng):Hitachi Semiconductor 功能描述:Digital Signal Processor for CD
HD49304ANT 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:8-Bit Digital-to-Analog Converter
HD49306AF 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Converter IC
HD49307 制造商:HITACHI 制造商全稱(chēng):Hitachi Semiconductor 功能描述:Three-Channel 8-bit D/A Converter
HD49307FB 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Converter IC
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