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參數(shù)資料
| 型號： | HD49235 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 16 AMP SPDT MINIATURE POWER RELAY |
| 中文描述： | 數(shù)字信號處理器的CD |
| 文件頁數(shù)： | 22/41頁 |
| 文件大小： | 192K |
| 代理商： | HD49235 |
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HD49235FS
Rev.2, Aug. 1995, page 22 of 41
Control of 16-kbit On-Chip SRAM
The demodulated EFM data is synchronized with the PLL clock, and its output timing may contain jitter
due to disturbances in the CLV servo that controls disc rotation. To absorb the jitter, the demodulated EFM
data is stored in the on-chip RAM, then read out in synchronization with a clock signal derived from the
crystal oscillator. The RAM capacity sets a limit on the amount of jitter that can be absorbed. In this chip, a
delay of ±5 frames between RAM read and write would lead to overwriting of existing data. The
overwritten data would be destroyed, making the reproduced sound unreliable.
To avoid this, if the read and write base counters get more than ±5 frames out of step, the write base
counter is set to the value of the read base counter and the frame jitter margin is set to the maximum, ±5
frames.
OVFW:
This pin outputs a high RAM overflow flag signal to indicate that the difference between the
read and write base counters exceeded ±5 frames and the write base counter was set to the value of the
read base counter.
MUTE:
This pin is used to force the audio data to the mute state.
When MUTE is low, muting is not performed.
When MUTE is high, muting is performed.
When MUTE goes high, the address control circuit is initialized so as to maximize the RAM frame jitter
margin at that point. This initialization is performed continuously while MUTE is high. Normal
reproduction resumes when MUTE goes low.
Error Correction Unit (ECU)
The error correction unit can correct two-symbol C1 errors and four-symbol C2 errors.
The results of C1 error correction are flagged by a C1 flag. Since two-symbol errors can be corrected, each
C1 correction produces a 2-bit C1 flag. The C1 flag data is written into an internal buffer RAM area and is
read out again during C2 correction.
C2 error correction is carried out using the calculated error locations and error values, and the C1 error
status and error positions indicated by the C1 error flags.
The interpolation block reads audio data and the corresponding C1 and C2 flags. If it decides from the C1
and C2 flags that the audio data is unreliable, it performs mean-value interpolation or preceding-value
interpolation.
TC1:
This pin outputs a signal indicating whether each frame of data read from the disc contained an
error. See figure 11 for the output timing.
High if no error
TC1
136 μs
354 ns
Figure 11 TC1 Timing (Standard Speed Playback)
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|---|---|
| HD49235FS | Digital Signal Processor for CD |
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| HD49307 | Three-Channel 8-bit D/A Converter |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HD49235FS | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:Digital Signal Processor for CD |
| HD49304ANT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Digital-to-Analog Converter |
| HD49306AF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Converter IC |
| HD49307 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:Three-Channel 8-bit D/A Converter |
| HD49307FB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Converter IC |
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