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參數(shù)資料
| 型號： | HD4074394S |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 4-bit HMCS400-series microcomputer(4位單片微計算機) |
| 中文描述： | 4位HMCS400系列微電腦（4位單片微計算機） |
| 文件頁數(shù)： | 67/100頁 |
| 文件大小： | 610K |
| 代理商： | HD4074394S |
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HD404344R Series/HD404394 Series
67
Notes On Use:
Initializing after writing to registers: If port mode register A (PMRA: $004) is written to in the transmit
clock wait state or transfer state, the serial interface should be reinitialized by writing to the serial mode
register (SMR: $005).
Serial interrupt request flag (IFS: $003, bit 2) set: For the serial interface, if the state is changed from
transfer state to another by writing to serial mode register (SMR:$005) or executing the STS instruction
during the first low pulse of the transmit clock, the serial interrupt request flag (IFS: $003, bit 2) is not
set. To set the serial interrupt request flag (IFS: $003, bit 2), a serial mode register (SMR: $005) write
or STS instruction execution must be programmed to be executed after confirming that the
SCK
pin is
at 1, that is, after executing the input instruction to port R0.
Registers for Serial Interface
The serial interface operation is selected, and serial data is read and written using the following registers:
Serial mode register (SMR: $005)
Port mode register C (PMRC: $025)
Serial data registers (SRL: $006 and SRU: $007)
Port mode register A (PMRA: $004)
Miscellaneous register (MIS: $00C)
Serial Mode Register (SMRA: $005):
This register has the following functions (figure 45):
R0
0
/
SCK
pin function selection
Selection of transmit clock
Selection of prescaler division ratio
Serial interface initialization
The write-only serial mode register is reset to $0 by an MCU reset. Writing to the serial mode register
discontinues the transmit clock input to the serial data registers (SRL: $006 and SRU: $007) and the octal
counter. The octal counter is then reset to 000. If the serial mode register is written to during serial interface
operation, data transfer will be cut off and the serial interrupt request flag (IFS: $003, bit 2) will be set.
Data in the serial mode register becomes effective after two instruction execution cycles from the time the
serial mode register is written to. It is therefore necessary to program the STS instruction to be executed
two cycles after the serial mode register is written to.
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