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參數(shù)資料
| 型號(hào)： | HD4074394S |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 4-bit HMCS400-series microcomputer(4位單片微計(jì)算機(jī)) |
| 中文描述： | 4位HMCS400系列微電腦（4位單片微計(jì)算機(jī)） |
| 文件頁(yè)數(shù)： | 66/100頁(yè) |
| 文件大?。?/td> | 610K |
| 代理商： | HD4074394S |
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HD404344R Series/HD404394 Series
66
Transmit Clock Error Detection (External Clock Mode):
Serial interface will malfunction if a spurious
pulse caused by external noise conflicts with a normal transmit clock during data transfer. A transmit clock
error of this type can be detected as shown in figure 44.
If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse
by noise, the octal counter reaches 000, the serial interrupt request flag (IFS: $003, bit 2) is set, and
transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is
entered. After the transfer is completed and IFS is reset, writing to the serial mode register (SMR: $005)
changes the state from transfer to STS wait. At this time the serial interface is in the transfer state, and the
serial interrupt request flag (IFS: $003, bit 2) is set again, and therefore the error can be detected.
Transfer completion
(IFS 1)
Interrupts inhibited
IFS 0
SMR write
IFS = 1
Transmit clock
error processing
Normal
termination
Yes
No
Transmit clock error detection flowchart
Transmit clock error detection procedure
State
SCK
pin (input)
Transmit clock
wait state
Transfer state
Transfer state
Transmit clock wait state
Noise
Transfer state has been
entered by the transmit
clock error. When SMR is
written, IFS is set.
Flag set because octal
counter reaches 000.
Flag reset at
transfer completion.
SMR write
IFS
1
2
3
4
5
6
7
8
Figure 44 Transmit Clock Error Detection
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相關(guān)代理商/技術(shù)參數(shù) |
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| HD4074408C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4-Bit Microcontroller |
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| HD4074408H | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4-Bit Microcontroller |
| HD4074408S | 制造商:Renesas Electronics Corporation 功能描述:HIT 4 BIT MICROCOMPUTER (ZTAT) |
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