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參數(shù)資料
| 型號(hào)： | HD4-15530-8 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | CMOS Manchester Encoder-Decoder |
| 中文描述： | DATACOM, MANCHESTER ENCODER/DECODER, CQCC28 |
| 文件頁(yè)數(shù)： | 4/12頁(yè) |
| 文件大?。?/td> | 169K |
| 代理商： | HD4-15530-8 |
5-145
Decoder Operation
The Decoder requires a single clock with a frequency of 12
times the desired data rate applied at the DECODER
CLOCK input. The Manchester II coded data can be
presented to the Decoder in one of two ways. The BIPOLAR
ONE and BIPOLAR ZERO inputs will accept data from a
comparator sensed transformer coupled bus as specified in
Military Spec 1553. The UNIPOLAR DATA input can only
accept non-inverted Manchester II coded data. (e.g. from
BIPOLAR ONE OUT of an Encoder through an inverter to
Unipolar Data Input).
The Decoder is free running and continuously monitors its
data input lines for a valid sync character and two valid
Manchester data bits to start an output cycle. When a valid
sync is recognized
, the type of sync is indicated on
COMMAND/DATA SYNC output. If the sync character was a
command sync, this output will go high
for sixteen DECODER SHIFT CLOCK periods
it will remain low. The TAKE DATA output will go high and
remain high
-
while the Decoder is transmitting the
decoded data through SERIAL DATA OUT. The decoded
and remain high
, otherwise
3
data available at SERIAL DATA OUT is in NRZ format. The
DECODER SHIFT CLOCK is provided so that the decoded
bits can be shifted into an external register on every low-to-
high transition of this clock
SHIFT CLOCK may adjust its phase up until the time that
TAKE DATA goes high.
-
. Note that DECODER
After all sixteen decoded bits have been transmitted
data is checked for odd parity. A high on VALID WORD
output
indicates a successful reception of a word without
any Manchester or parity errors. At this time the Decoder is
looking for a new sync character to start another output
sequence. VALID WORD will go low approximately 20
DECODER SHIFT CLOCK periods after it goes high if not
reset low sooner by a valid sync and two valid Manchester
bits as shown
.
1
the
At any time in the above sequence a high input on
DECODER RESET during a low-to-high transition of
DECODER SHIFT CLOCK will abort transmission and ini-
tialize the Decoder to start looking for a new sync character.
1
2
2
3
2
3
3
4
FIGURE 2.
UNDEFINED
P
0
1
2
P
0
1
2
1
2
3
4
0
16
17
18
19
7
6
5
4
11
12
13
14
15
11
12
13
14
15
12
13
14
15
SYNC
SYNC
2ND HALF
1ST HALF
3
2
1
0
TIMING
DECODER
SHIFT CLK
COMMAND/
DATA SYNC
TAKE DATA
SERIAL
DATA OUT
8
10
10
1
2
3
4
BIPOLAR
ONE IN
BIPOLAR
ZERO IN
(FROM PREVIOUS RECEPTION)
VALID WORD
HD-15530
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| HD4-15530-9 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Manchester Encoder-Decoder |
| HD4-15530B6175 | 制造商:Harris Corporation 功能描述: |
| HD4-15531-2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
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