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參數(shù)資料
| 型號： | HD1-15531 |
| 英文描述： | ENCODER/DECODER|CMOS|DIP|40PIN|CERAMIC |
| 中文描述： | 編碼/解碼器|的CMOS |雙酯| 40PIN |陶瓷 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 278K |
| 代理商： | HD1-15531 |
6
ting the decoded data through SERIAL DATA OUT. The
decoded data available at SERIAL DATA OUT is in NRZ
format. The DECODER SHIFT CLOCK is provided so that
the decoded bits can get shifted into an external register on
every low-to-high transition of this clock
DECODER SHIFT CLOCK may adjust its phase up until the
time that TAKE DATA goes high.
-
. Note that
After all K decoded bits have been transmitted
checked for parity. A high input on DECODER PARITY
SELECT will set the Decoder to check for even parity or a
low input will set the Decoder to check for odd parity. A high
the data is
on VALID WORD output
of a word without any Manchester or parity errors. At this
time the Decoder is looking for a new sync character to start
another output sequence. VALID WORD will go low approx-
imately K + 4 DECODER SHIFT CLOCK periods after it
goes high, if not reset low sooner by a valid sync and two
valid Manchester bits as shown
indicates a successful reception
.
At any time in the above sequence a high input on
DECODER RESET during a low-to-high transition of
DECODER SHIFT CLOCK will abort transmission and ini-
tialize the Decoder to start looking for a new sync character.
2
3
3
4
1
SERIAL
DATA OUT
1ST HALF
TIMING
SYNCHRONOUS
CLOCK
DECODER
SHIFT
CLOCK
BIPOLAR
ONE IN
BIPOLAR
ZERO IN
TAKE DATA
2ND HALF
SYNC
SYNC
MSB
MSB
BITK-1
BITK-1
BITK-2
BITK-2
BITK-3
BITK-3
BITK-5
BITK-4 BITK-5
BITK-4
0
1
2
3
4
5
6
7
8
N-3
N-2
N-1
N
BIT 3
BIT 2
PARITY
BIT 1
BIT 2
BIT 3
BIT 1 PARITY
BITK-1
VALID WORD
DATA SYNC
COMMAND
SYNC
MSB
BITK-2 BITK-3
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
3
4
2
1
(MAY BE HIGH FROM PREVIOUS RECEPTION)
UNDEFINED
FIGURE 2. DECODER
HD-15531
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HD1-15531B-2 | Encoder/Decoder |
| HD1-6402B-9 | CMOS Universal Asynchronous Receiver Transmitter (UART) |
| HD1-6402R-9 | CMOS Universal Asynchronous Receiver Transmitter (UART) |
| HD3-6402B-9 | CMOS Universal Asynchronous Receiver Transmitter (UART) |
| HD3-6402R-9 | CMOS Universal Asynchronous Receiver Transmitter (UART) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HD1-15531/883 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Manchester Encoder-Decoder |
| HD1-15531-2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| HD1-15531-8 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Manchester Encoder-Decoder |
| HD1-15531-9 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HD1-15531B | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Manchester Encoder-Decoder |
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