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參數(shù)資料
| 型號： | HD-15531883 |
| 廠商： | Intersil Corporation |
| 英文描述： | SCR Thyristor; SCR Type:Sensitive Gate; Peak Repetitive Off-State Voltage, Vdrm:30V; On-State RMS Current, IT(rms):4A; Peak Non Repetitive Surge Current, Itsm:20A; Gate Trigger Current Max, Igt:50uA |
| 中文描述： | 的CMOS曼徹斯特編碼，解碼器 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 115K |
| 代理商： | HD-15531883 |
5-175
Take Data
Delay (ON)
TD7
VCC = 4.5V and 5.5V
9, 10, 11
-55
o
C
≤
T
A
≤
+125
o
C
0
110
0
110
ns
Serial Data
Out Delay
TD8
VCC = 4.5V and 5.5V
9, 10, 11
-55
o
C
≤
T
A
≤
+125
o
C
-
80
-
80
ns
Sync Delay
(OFF)
TD9
VCC = 4.5V and 5.5V
9, 10, 11
-55
o
C
≤
T
A
≤
+125
o
C
0
110
0
110
ns
Take Data
Delay (OFF)
TD10
VCC = 4.5V and 5.5V
9, 10, 11
-55
o
C
≤
T
A
≤
+125
o
C
0
110
0
110
ns
Valid Word
Delay
TD11
VCC = 4.5V and 5.5V
9, 10, 11
-55
o
C
≤
T
A
≤
+125
o
C
0
110
0
110
ns
Sync Clock to
Shift Clock
Delay
TD12
VCC = 4.5V and 5.5V
9, 10, 11
-55
o
C
≤
T
A
≤
+125
o
C
-
75
-
75
ns
Sync Data
Setup
TD13
VCC = 4.5V and 5.5V
9, 10, 11
-55
o
C
≤
T
A
≤
+125
o
C
75
-
75
-
ns
NOTES:
1. TDC = Decoder Clock Period = 1/FDC.
2. AC Testing as follows: VIH = 70% VCC, VIL = 20% VCC; Input rise/fall times driven at 1ns/V; Timing reference levels: VCC/2;
Output load: CL = 50pF.
TABLE 2. HD-15531/883, HD-15531B/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
PARAMETER
SYMBOL
(NOTE 2)
CONDI-TIONS
GROUP A
SUB-
GROUPS
TEMPERATURE
HD-15531/883
HD-15531B/883
UNITS
MIN
MAX
MIN
MAX
TABLE 3. HD-15531/883, HD-15531B/883 ELECTRICAL PERFORMANCE SPECIFICATIONS
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
T
A
= +25
o
C
LIMITS
UNITS
MIN
MAX
Input Capacitance
CI
VCC = OPEN, f = 1MHz, All measure-
ments referenced to device GND
1
-
25
pF
Input/Output Capaci-
tance
CIO
VCC = OPEN, f = 1MHz, All measure-
ments referenced to device GND
1
T
A
= +25
o
C
-
25
pF
Operating Power
Supply Current
ICCOP
VCC = 5.5V, f = 1MHz
1, 2
-55
o
C
≤
T
A
≤
+125
o
C
-
10
mA
NOTES:
1. The parameters listed in Table 3 are controlled via design or process parameters are characterized upon initial design and after major
process and/or design changes.
2. Guaranteed but not 100% tested.
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
METHOD
SUBGROUPS
Initial Test
100%/5004
-
Interim Test
100%/5004
1, 7, 9
PDA
100%/5004
1
Final Test
100%/5004
2, 3, 8A, 8B, 10, 11
Group A
Samples/5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Groups C & D
Samples/5005
1, 7, 9
HD-15531/883
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