參數(shù)資料
型號： HCPL-9030
英文描述： High Speed Digital Isolators
中文描述： 高速數(shù)字隔離器
文件頁數(shù)： 9/12頁
文件大?。?/td> 449K
代理商： HCPL-9030
9
Electrical Specifications
Test conditions that are not specified can be anywhere within the recommended operating range.
All typical specifications are at T
A
=+25
°
C, V
DD1
= V
DD2
= +5.0V.
Parameter
Symbol
Min.
Typ.
Max.
Units Test Conditions
Quiescent Supply Current 1
I
DD1
mA
V
IN
= 0V
HCPL-9000/-0900
HCPL-9030/-0930
HCPL-9031/-0931
HCPL-900J/-090J
HCPL-901J/-091J
HCPL-902J/-092J
0.012
0.012
2.5
0.024
5.0
2.5
0.018
0.018
3.0
0.036
6.0
3.0
Quiescent Supply Current 2
I
DD2
mA
V
IN
= 0V
HCPL-9000/-0900
HCPL-9030/-0930
HCPL-9031/-0931
HCPL-900J/-090J
HCPL-901J/-091J
HCPL-902J/-092J
5.0
5.0
2.5
8.0
5.0
6.0
6.0
6.0
3.0
12.0
6.0
9.0
Logic Input Current
I
IN
-10
10
μ
A
Logic High Output Voltage
V
OH
V
DD2
–
0.1
V
DD2
V
I
OUT
= -20
μ
A, V
IN
= V
IH
0.8*V
DD2
V
DD2
–
0.5
V
I
OUT
= -4 mA, V
IN
= V
IH
Logic Low Output Voltage
V
OL
0
0.1
V
I
OUT
= 20
μ
A, V
IN
= V
IL
0.5
0.8
V
I
OUT
= 4 mA, V
IN
= V
IL
Switching Specifications
Maximum Data Rate
100
110
MBd
C
L
= 15 pF
Clock Frequency
fmax
50
MHz
Propagation Delay Time to Logic
Low Output
t
PHL
10
15
ns
Propagation Delay Time to Logic
High Output
t
PLH
10
15
ns
Pulse Width
t
PW
10
ns
Pulse Width Distortion
[1]
|t
PHL
–
t
PLH
|
|PWD|
2
3
ns
Propagation Delay Skew
[2]
t
PSK
4
6
ns
Output Rise Time (10
–
90%)
t
R
1
3
ns
Output Fall Time (10
–
90%)
t
F
1
3
ns
Propagation Delay Enable to Output (Single Channel)
High to High Impedance
t
PHZ
3
5
ns
Low to High Impedance
t
PLZ
3
5
ns
High Impedance to High
t
PZH
3
5
ns
High Impedance to Low
t
PZL
3
5
ns
Channel-to-Channel Skew
(Dual and Quad Channels)
t
CSK
2
3
ns
Common Mode Transient Immunity
(Output Logic High or Logic Low)
[3]
|CM
H
|
|CM
L
|
15
18
kV/
μ
s
V
cm
= 1000V
Notes:
1. PWD is defined as |t
PHL
-t
PLH
|. %PWD is equal to the PWD divided by the pulse width.
2. t
PSK
is equal to the magnitude of the worst case difference in t
PHL
and/or t
PLH
that will be seen between units at 25
°
C.
3. CM
H
is the maximum common mode voltage slew rate that can be sustained while maintaining V
OUT
> 0.8V
DD2
. CM
L
is the maximum common mode
input voltage that can be sustained while maintaining V
OUT
< 0.8V. The common mode voltage slew rates apply to both rising and falling common mode
voltage edges.
This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Agilent recommends that all integrated circuits
be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to
complete failure.
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