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參數(shù)資料
| 型號： | HCD66751BP |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 128 x 128-dot Graphics LCD Controller/Driver with Four-grayscale Functions |
| 中文描述： | 128 × 128點圖形LCD控制器/驅動器，四灰度函數(shù) |
| 文件頁數(shù)： | 38/96頁 |
| 文件大小： | 2068K |
| 代理商： | HCD66751BP |
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Table 16 Instruction List
Reg.
Upper Code
Lower Code
No.
Register Name
R/W
RS
DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Description
IR
Index
0
0
*
*
*
*
*
*
*
*
*
*
*
ID4
ID3
ID2
ID1
ID0
Sets the index register value.
0
SR
Status read
1
0
0
L6
L5
L4
L3
L2
L1
L0
0
0
C5
C4
C3
C2
C1
C0
Reads the driving raster-row position (L6D0) and contrast setting (C5D0).
0
R00
Start oscillation
0
1
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
Starts the oscillation mode.
10 ms
Device code read
1
1
0
0
0
0
0
1
1
1
0
1
0
1
0
0
0
0
Reads 0750H.
0
R01
Driver output
0
1
*
*
*
*
*
*
CMS SGS
*
CN
*
*
NL3
NL2
NL1
NL0
Sets the common driver shift direction (CMS), segment driver shift direction
0
control
(SGS), driving duty ratio (NL3D0), and centering (CN).
R02
LCD-driving-
0
1
*
*
*
*
*
*
*
*
*
B/C
EOR NW4 NW3 NW2 NW1 NW0 Sets the LCD drive AC waveform (B/C), and EOR output (EOR) or the
0
waveform control
number of n-raster-rows (NW4D0) at C-pattern AC drive.
R03
Power control
0
1
*
*
*
BS2
BS1
BS0
BT1
BT0
*
*
DC1 DC0
AP1
AP0
SLP
STB
Sets the sleep mode (SLP), standby mode (STB), LCD power on (AP1D0),
0
boosting cycle (DC1D0), boosting ouput multiplying factor (BT1D0), and LCD
drive bias value (BS2D0).
R04
Contrast control
0
1
*
*
*
*
*
*
*
*
*
*
CT5
CT4
CT3
CT2
CT1
CT0
Sets the contrast adjustment (CT5D0).
0
R05
Entry mode
0
1
*
*
*
*
*
*
*
*
*
*
*
I/D
AM1 AM0
LG1
LG0
Specifies the logical operation (LG1D0), AC counter mode (AM1D0), and
0
increment/decrement mode (I/D).
R06
Rotation
0
1
*
*
*
*
*
*
*
*
*
*
*
*
*
RT2
RT1
RT0
Specifies the amount of write-data rotation (RT2D0).
0
R07
Display control
0
1
*
*
*
*
*
*
*
*
*
*
PS1
PS0 DHE
GS
REV
D
Specifies display on (D), black-and-white reversed display (REV), grayscale
0
mode (GS), double-height display on (DHE), and partial scroll (PS1D0).
R08
Cursor control
0
1
*
*
*
*
*
*
*
*
*
*
*
*
*
C
CM1 CM0 Specifies cursor display on (C) and cursor display mode (CM1D0).
R09
Double-height display position
0
1
*
DE6
DE5
DE4
DE3
DE2
DE1
DE0
*
DS6
DS5
DS4
DS3
DS2
DS1
DS0
Specifies double-height display start (DS6D0) and end (DE6D0).
0
R0A
Vertical scroll
0
1
*
*
*
*
*
*
*
*
*
SL6
SL5
SL4
SL3
SL2
SL1
SL0
Sets the display-start raster-row (SL6D0).
0
R0B
Horizontal cursor position
0
1
*
HE6
HE5
HE4
HE3
HE2
HE1
HE0
*
HS6
HS5
HS4
HS3
HS2
HS1
HS0
Sets horizontal cursor start (HS6D0) and end (HE6D0).
0
R0C
Vertical cursor position
0
1
*
VE6
VE5
VE4
VE3
VE2
VE1
VE0
*
VS6
VS5
VS4
VS3
VS2
VS1
VS0
Sets vertical cursor start (VS6D0) and end (VE6D0).
0
R10
RAM write data
0
1
WM
WM
WM
WM
WM
WM WM9 WM8 WM7 WM6 WM5 WM4 WM3 WM2 WM1 WM0 Specifies write data mask (WM15D0) at RAM write.
0
mask
15
14
13
12
11
10
R11
RAM address set
0
1
*
*
*
*
*
AD10D8 (upper)
AD7D0 (lower)
Initially sets the RAM address to the address counter (AC).
0
R12
RAM data write
0
1
Write data (upper)
Write data (lower)
Writes data to the RAM.
0
RAM data read
1
1
Read data (upper)
Read data (lower)
Reads data from the RAM.
0
Note: '*' means 'doesn't matter'.
Execu-
tion
Cycle
HITACHI
38
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