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參數(shù)資料
| 型號： | HCD66750BP |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 128 x 128-dot Graphics LCD Controller/Driver with Four-grayscale Functions |
| 中文描述： | 128 × 128點圖形LCD控制器/驅(qū)動器，四灰度函數(shù) |
| 文件頁數(shù)： | 37/96頁 |
| 文件大?。?/td> | 2068K |
| 代理商： | HCD66750BP |
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HD66750/1
37
Read Data from CGRAM
RD15-0 :
Read 16-bit data from the CGRAM. When the data is read to the microcomputer, the first-word
read immediately after the CGRAM address setting is latched from the CGRAM to the internal read-data
latch. The data on the data bus (DB15D0) becomes invalid and the second-word read is normal.
When bit processing, such as a logical operation, is performed within the HD66750/1, only one read can be
processed since the latched data in the first word is used.
1
1
R/W
RS
DB7
DB0
DB6 DB5
DB4 DB3
DB2
DB1
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
RD
15
RD
14
RD
13
RD
12
RD
11
RD
10
RD
9
RD
8
RD
7
RD
6
RD
5
RD
4
RD
3
RD
2
RD
1
RD
0
Figure 20 Read Data from CGRAM Instruction
Address: N set
Dummy read (invalid data)
CGRAM -> Read-data latch
Read (data of address n)
Read-data latch -> DB15D0
First word
Second word
i) Data read to the microcomputer
ii) Logical operation processing in the HD66750/1
Address: M set
Dummy read (invalid data)
CGRAM -> Read-data latch
Read (data of address)
Read-data latch -> DB15D0
First word
Second word
Sets the I/D and AM1D0 bits
Address: N set
Dummy read (invalid data)
CGRAM -> Read-data latch
Sets the I/D and AM1D0 bits
Read (data of address n)
DB15D0 -> CGRAM
Dummy read (invalid data)
CGRAM -> Read-data latch
Write (data of address n)
DB15D0 -> CGRAM
Automatic address update: M +
α
First word
Second word
First word
Second word
Figure 21 CGRAM Read Sequence
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