參數(shù)資料
型號(hào)： HCD66712UA03
廠商： Hitachi,Ltd.
英文描述： Dot-Matrix Liquid Crystal Display Controller/Driver
中文描述： 點(diǎn)陣液晶顯示控制器/驅(qū)動(dòng)器
文件頁(yè)數(shù)： 45/88頁(yè)
文件大?。?/td> 662K
代理商： HCD66712UA03
HD66712U
408
RE:
When bit RE is 1, bit BE in the extended function set register, the SEGRAM address set register,
and the function set register can be accessed. When bit RE is 0, the registers described above cannot be
accessed, and the data in these registers is held.
To maintain compatibility with the HD44780, the RE bit should be fixed to 0.
Table 10
Shift Function
S/C
R/L
0
0
Shifts the cursor position to the left. (AC is decremented by one.)
0
1
Shifts the cursor position to the right. (AC is incremented by one.)
1
0
Shifts the entire display to the left. The cursor follows the display shift.
1
1
Shifts the entire display to the right. The cursor follows the display shift.
BE:
When the RE bit is 1, this bit can be rewritten. When this bit is 1, the user font in CGRAM and the
segment in SEGRAM can be blinked according to the upper two bits of CGRAM and SEGRAM.
LP:
When bit RE is 1, this bit can be rewritten. When LP is set to 1 and the EXT pin is low (without an
extended driver), the HD66712 operates in low power mode. In 1-line display mode, the HD66712
operates on a 4-division clock, and in a 2-line or a 4-line display mode, the HD66712 operates on a 2-
division clock. According to these operations, instruction execution takes four times or twice as long.
Note that in low power mode, display shift cannot be performed. The frame frequency is reduced to 5/6
that of normal operation. See “Oscillator Circuit” for details.
Note:
Perform the DL, N, NW, and FW fucntions at the head of the program before executing any
instructions (except for the read busy flag and address instruction). From this point, if bits N,
NW, or FW are changed after other instructions are executed, RAM contents may be broken.
Set CGRAM Address
A CGRAM address can be set while the RE bit is cleared to 0.
Set CGRAM address into the address counter displayed by binary AAAAAA. After this address set, data
is written to or read from the MPU for CGRAM.
Set SEGRAM Address
Only when the extended register enable (RE) bit is 1, HS2 to HS0 and the SEGRAM address can be set.
The SEGRAM address in the binary form AAAA is set to the address counter. After this address set,
SEGRAM can be written to or read from by the MPU.
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