參數(shù)資料
型號(hào)： HCD66712UA03
廠商： Hitachi,Ltd.
英文描述： Dot-Matrix Liquid Crystal Display Controller/Driver
中文描述： 點(diǎn)陣液晶顯示控制器/驅(qū)動(dòng)器
文件頁數(shù)： 14/88頁
文件大小： 662K
代理商： HCD66712UA03
HD66712U
377
Function Description
System Interface
The HD66712 has three types of system interfaces: synchronized serial, 4-bit bus, and 8-bit bus. The
serial interface is selected by the IM-pin, and the 4/8-bit bus interface is selected by the DL bit in the
instruction register.
The HD66712 has two 8-bit registers: an instruction register (IR) and a data register (DR).
The IR stores instruction codes, such as display clear and cursor shift, and address information for the
display data RAM (DDRAM), the character generator RAM (CGRAM), and the segment RAM
(SEGRAM). The MPU can only write to IR, and cannot be read from.
The DR temporarily stores data to be written into DDRAM, CGRAM, or SEGRAM. Data written into the
DR from the MPU is automatically written into DDRAM, CGRAM, or SEGRAM by an internal
operation. The DR is also used for data storage when reading data from DDRAM, CGRAM, or
SEGRAM. When address information is written into the IR, data is read and then stored into the DR from
DDRAM or CGRAM by an internal operation. Data transfer between the MPU is then completed when
the MPU reads the DR. After the read, data in DDRAM, CGRAM, or SEGRAM at the next address is
sent to the DR for the next read from the MPU.
These two registers can be selected by the registor selector (RS) signal in the 4/8 bit bus interface, and by
the RS bit in start byte data in synchronized serial interface (Table 2).
Busy Flag (BF)
When the busy flag is 1, the HD66712 is in the internal operation mode, and the next instruction will not
be accepted. When RS = 0 and R/W = 1 (Table 2), the busy flag is output from DB7. The next instruction
must be written after ensuring that the busy flag is 0.
Address Counter (AC)
The address counter (AC) assigns addresses to DDRAM, CGRAM, or SEGRAM. When an address of an
instruction is written into the IR, the address information is sent from the IR to the AC. Selection of
DDRAM, CGRAM, and SEGRAM is also determined concurrently by the instruction.
After writing into (reading from) DDRAM, CGRAM, or SEGRAM, the AC is automatically incremented
by 1 (decremented by 1). The AC contents are then output to DB0 to DB6 when RS = 0 and R/
:
= 1
(Table 2).
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