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參數(shù)資料
| 型號： | HC55142IMZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 17/36頁 |
| 文件大小： | 0K |
| 描述： | IC SLIC UNIVERSAL LP 28-PLCC |
| 標(biāo)準(zhǔn)包裝： | 37 |
| 系列： | UniSLIC14 |
| 功能： | 用戶線路接口概念（SLIC） |
| 電路數(shù)： | 1 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 電流 - 電源： | 2.25mA |
| 功率（瓦特）： | 1.5W |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 管件 |
| 包括： | 電池跟蹤抗削頂失真，回路和接地鍵檢測，振鈴控制 |
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24
FN4659.13
June 1, 2006
Loopback Tests
4-Wire Loopback Test
This feature can be very useful in the testing of line cards
during the manufacturing process and in field use. The test
is unobtrusive, allowing it to be used in live systems.
Reference Figure 22.
Most systems do not provide 4-wire loopback test capability
because of costly relays needed to switch in external loads.
All the SLICs in the UniSLIC14 family can easily provide
this function when configured in the Open Circuit logic
state. With the PTG pin floating, the signal on the VTX
output is 180° out of phase and approximately 2 times the
VRX input signal. If the PTG pin is grounded, then the
amplitude will be approximately the same as the input
signal and 180° out of phase.
2-Wire Loopback Test
Most of the SLICs in the UniSLIC14 family feature 2-Wire
loopback testing. This loopback function is only activated
when the subscriber is on hook and the logic command to
the SLIC is in the Test Active State. (Note: if the subscriber is
off hook and in the Test Active State, the function performed
is the Line Voltage Measurement.)
During the 2-wire loopback test, a 2k
internal resistor is
switched across the tip and ring terminals of the SLIC. This
allows the SHD function and the 4-wire to 4-wire AC
transmission, right up to the subscriber loop, to be tested.
Together with the 4-wire loopback test in the Open Circuit
logic state, this 2-wire loopback test allows the complete
network (including SLIC) to be tested up to the subscriber
loop.
Pulse Metering
The HC55121, HC55142, HC35143, and HC55150 are
designed to support pulse metering. They offer solutions to
the following pulse metering design issues:
1) Providing adequate signal gain and current drive to the
subscriber metering equipment to overcome the attenuation
of this (12kHz, 16kHz) out of band signal.
2) Attenuating the pulse metering transhybrid signal without
severely attenuating the voice band signal to avoid clipping
in the CODEC/Filter.
3) Tailoring the overload levels in the SLIC to avoid clipping
of the combined voiceband and pulse metering signal.
4) Having the provision of silent polarity reversal as a backup
in the case where the loop attenuates the out of band signal
too much for it to be detected by the subscriber’s metering
equipment.
Adequate Signal Gain
Adequate signal gain and current drive to the subscriber’s
metering equipment is made easier by the network shown in
Figure 23. The pulse metering signal is supplied to a
dedicated high impedance input pin called SPM. The circuit
in Figure 23 shows the connection of a network that sets the
2-wire impedance (ZTR), at the pulse metering frequencies,
to be approximately 200
. If the line impedance (Z
L) is equal
to 200
at the pulse metering frequencies, then the 4-Wire
to 2-wire gain (VTR/SPM) is equal 4. Thereby lowering the
input signal requirements of the pulse metering signal.
Note: The automatic pulse metering 2-wire impedance
matching is independent of the programmed 2-wire
impedance matching at voiceband frequencies.
Calculation of the pulse metering gain is achieved by
replacing VRX/500k in Equation 15 with SPM/125k and
following the same process through to Equation 21. The
UniSLIC14 sets the 2-wire input impedance of the SLIC
(ZTR), including the protection resistors, equal to 200. The
results are shown in Equation 41.
Avoiding Clipping in the CODEC/Filter
The amplitude of the returning pulse metering signal is often
very large and could easily over drive the input to the
CODEC/Filter. By using the same method discussed in
section “Transhybrid Balance”, most if not all of the pulse
metering signal can be canceled out before it reaches the
input to the CODEC/Filter. This connection is shown in
Figure 23.
FIGURE 21. TRANSHYBRID BALANCE USING THE PTG PIN
VTX
VRX
VTX
-
+
VRX
+
-
500K
PTG
+
-
IX
5
A = 1
IX
R1
R2
500K
UniSLIC14
FIGURE 22.
4-WIRE AND 2-WIRE LOOPBACK TESTS
VTX
VRX
TIP
RING
4-WIRE LOOPBACK
UniSLIC14
600
DUAL SUPPLY
CODEC/FILTER
INTERNAL
2-WIRE LOOPBACK
+
-
PTG
A
4-2 =
V
TR
SPM
------------- = 8
–
Z
L
Z
L + ZTR
-------------------------
8
200
200 + 200
---------------------------
–
4
–
==
(EQ. 41)
HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150
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| HC55142IMZ96 | 功能描述:電信線路管理 IC HC55142IM IN TAPE RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| HC55143 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Low Power Universal SLIC Family |
| HC55143IM | 功能描述:IC SLIC UNIVERSAL LP 32-PLCC RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:UniSLIC14 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:* |
| HC5514X | 制造商:Harris Corporation 功能描述: |
| HC5514XB | 制造商:Harris Corporation 功能描述: |
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