參數(shù)資料
型號(hào): HB52E649E12-A6B
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 512 MB Registered SDRAM DIMM 64-Mword 】 72-bit, 100 MHz Memory Bus, 1-Bank Module (18 pcs of 64 M 】 4 Components) PC100 SDRAM
中文描述: 64M X 72 SYNCHRONOUS DRAM MODULE, 6.9 ns, DMA168
封裝: DIMM-168
文件頁數(shù): 11/16頁
文件大?。?/td> 147K
代理商: HB52E649E12-A6B
HB52E649E12-A6B/B6B
Data Sheet E0020H20
11
Capacitance
(Ta = 25
°
C, V
CC
= 3.3 V ± 0.3 V)
Parameter
Symbol
Max
Unit
Notes
Input capacitance (Address)
Input capacitance (
RE
,
CE
,
W
)
C
I1
C
I2
C
I3
C
I4
C
I5
C
I6
C
I/O1
15
pF
1, 2, 4
15
pF
1, 2, 4
Input capacitance (CKE)
Input capacitance (
S
)
23
pF
1, 2, 4
15
pF
1, 2, 4
Input capacitance (CK)
40
pF
1, 2, 4
Input capacitance (DQMB)
15
pF
1, 2, 4
Input/Output capacitance (DQ)
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing.
3. DQMB = V
IH
to disable Data-out.
4. This parameter is sampled and not 100% tested.
15
pF
1, 2, 3, 4
AC Characteristics
(Ta = 0 to 55
°
C, V
CC
= 3.3 V ± 0.3 V, V
SS
= 0 V)
HB52E649E12
-A6B/B6B
Parameter
Symbol
PC100
Symbol
Min
Max
Unit
Notes
System clock cycle time
(
CE
latency = 3)
(
CE
latency = 4)
t
CK
Tclk
10
ns
1
t
CK
t
CKH
t
CKL
t
AC
Tclk
10
ns
CK high pulse width
Tch
4
ns
1
CK low pulse width
Tcl
4
ns
1
Access time from CK
(
CE
latency = 3)
(
CE
latency = 4)
Tac
6.9
ns
1, 2
t
AC
t
OH
t
LZ
t
HZ
t
DS
t
DH
t
AS
t
AH
t
CES
t
CESP
t
CEH
Tac
6.9
ns
Data-out hold time
Toh
2.1
ns
1, 2
CK to Data-out low impedance
1.1
ns
1, 2, 3
CK to Data-out high impedance
6.9
ns
1, 4
Data-in setup time
Tsi
2.9
ns
1
Data in hold time
Thi
1.9
ns
1
Address setup time
Tsi
2.6
ns
1
Address hold time
Thi
1.6
ns
1, 5
CKE setup time
Tsi
2.6
ns
1, 5
CKE setup time for power down exit
Tpde
2.6
ns
1
CKE hold time
Thi
1.6
ns
1
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