參數(shù)資料
型號： HB28B128MM2
廠商： Hitachi,Ltd.
英文描述： MultiMediaCard 16 Mbyte/32 Mbyte/64 Mbyte/128 MByte
中文描述： 多媒體16 Mbyte/32 Mbyte/64 Mbyte/128字節(jié)
文件頁數(shù)： 49/88頁
文件大小： 329K
代理商： HB28B128MM2
HB28E016/D032/D064/B128MM2
49
The host command and the card response are clocked out with the rising edge of the host clock. The delay
between host command and card response is N
CR
clock cycles. The following timing diagram is relevant
for host command CMD3:
S T content CRC E Z * * * * * * Z
CMD
Host command
S T content CRC E Z Z Z
Response
N
CR
cycles
Host active
Card active
Command Response Timing
(Identification Mode)
There is just one Z bit period followed by P bits pushed up by the responding card. The following timing
diagram is relevant for all host commands followed by a response, except CMD1, CMD2 and CMD3:
S T content CRC E Z Z P * * * P
CMD
Host command
S T content CRC E Z Z Z
Response
Card active
N
CR
cycles
Host active
Command Response Timing
(Data Transfer Mode)
Card identification and card operation conditions timing
The card identification (CMD2) and card operation condition (CMD1) timing are processed in the open-
drain mode. The card response to the host command starts after exactly N
ID
clock cycles.
S T content CRC E Z * * * Z
CMD
Host command
S T content
Z Z Z
CID or OCR
N
ID
cycles
Host active
Card active
Identification Timing
(Card Identification Mode)
Last card response - next host command timing
After receiving the last card response, the host can start the next command transmission after at least N
RC
clock cycles. This timing is relevant for any host command.
S T content CRC E Z * * * * * * Z
CMD
Response
S T content CRC E
Host command
N
RC
cycles
Card active
Host active
Timing Response End to Next CMD Start
(Data Transfer Mode)
相關(guān)PDF資料
PDF描述
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