參數(shù)資料
型號(hào): HB28B128MM2
廠商: Hitachi,Ltd.
英文描述: MultiMediaCard 16 Mbyte/32 Mbyte/64 Mbyte/128 MByte
中文描述: 多媒體16 Mbyte/32 Mbyte/64 Mbyte/128字節(jié)
文件頁數(shù): 37/88頁
文件大?。?/td> 329K
代理商: HB28B128MM2
HB28E016/D032/D064/B128MM2
37
Multiple block write with pre-defined block count
The card will transfer the requested number of data blocks, terminate the transaction and return to
transfer state. Stop command is not required at the end of this type of multiple block write, unless
terminated with an error. In order to start a multiple block write with pre-defined block count, the
host must use the SET_BLOCK_COUNT command (CMD23) immediately preceding the
WRITE_MULTIPLE_BLOCK (CMD25) command. Otherwise the card will start an open-ended
multiple block write which can be stopped using the STOP_TRANSMISSION command.
The host can abort writing at any time, within a multiple block operation, regardless of the its type.
Transaction abort is done by sending the stop transmission command. If a multiple block write with
predefined block count is aborted, the data in the remaining blocks is not defined.
f the card detects an error (e.g. write protect violation, out of range, address misalignment, internal error,
etc.) during a multiple block write operation (both types) it will ignore any further incoming data blocks
and remain in the Receive State. The host must than abort the operation by sending the stop transmission
command. The write error is reported in the response to the stop transmission command.
f the host sends a stop transmission command after the card received the last block of a multiple block
write with a pre-defined number of blocks, it will be responded to as an illegal command, since the card is
no longer in rcv state.
f the host uses partial blocks whose accumulated length is not block aligned and block misalignment is not
allowed (CSD parameter WRITE_BLK_MISALIGN is not set), the card will detect the block misalignment
error and abort programming before the beginning of the first misaligned block. The card will set the
ADDRESS_ERROR error bit in the status register, and wait (in the Receive-data-State) for a stop
command while ignoring all further data transfer. The write operation will also be aborted if the host tries
to write over a write-protected area. In this case, however, the card will set the WP_VIOLATION bit.
Programming of the CID and CSD register does not require a previous block length setting. The
transferred data is also CRC protected.
Erase
t is desirable to erase as many sectors at a time as possible in order to enhance the data throughput.
Identification of these sectors is accomplished with the TAG_* commands. Either an arbitrary set of
sectors within a single erase group, or an arbitrary selection of erase groups may be erased at one time, but
not both together. That is, the unit of measure for determining an erase is either a sector or an erase group,
but if a sector, all selected sectors must lie within the same erase group. To facilitate selection, a first
command with the starting address is followed by a second command with the final address, and all sectors
within this range will be selected for erase. After a range is selected, an individual sector (or group) within
that range can be removed using the UNTAG command. The host must adhere to the following command
sequence; TAG_SECTOR_START, TAG_SECTOR_END, UNTAG_SECTOR (up to 16 untag sector
commands can be sent for one erase cycle) and ERASE (or the same sequence for group tagging). The
following exception conditions are detected by the card: An erase or tag/untag command is received out of
sequence. The card will set the ERASE_SEQUENCE error bit in the status register and reset the whole
sequence. An out of sequence command (except SEND_STATUS) is received. The card will set the
ERASE_RESET status bit in the status register, reset the erase sequence and execute the last command. If
the erase range includes write protected sectors, they will be left intact and only the non-protected sectors
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