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參數(shù)資料
| 型號： | HAL800UT-A |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 英文描述： | Programmable Linear Hall Effect Sensor |
| 中文描述： | 可編程線性霍爾效應(yīng)傳感器 |
| 文件頁數(shù)： | 19/24頁 |
| 文件大小： | 347K |
| 代理商： | HAL800UT-A |
HAL800
Micronas
19
5. Programming of the Sensor
5.1. Definition of Programming Pulses
The sensor is addressed by modulating a serial tele-
gram on the supply voltage. The sensor answers with a
serial telegram on the output pin.
The bits in the serial telegram have a different Bit time
for the V
DD
-line and the output. The Bit time for the
V
DD
-line is defined through the length of the Sync Bit
at the beginning of each telegram. The Bit time for the
output is defined through the Acknowledge Bit.
A logical 0 is coded as no voltage change within the Bit
time. A logical 1 is coded as a voltage change between
50% and 80% of the Bit time. After each bit a voltage
change occurs.
5.2. Definition of the Telegram
Each telegram starts with the Sync Bit (logical 0), 3
bits for the Command (COM), the Command Parity Bit
(CP), 4 bits for the Address (ADR), and the Address
Parity Bit (AP).
There are 3 kinds of telegrams:
–
Write a register (see
Fig. 5
–
2
)
After the AP Bit follow 14 Data Bits (DAT) and the
Data Parity Bit (DP). If the telegram is valid and the
command has been processed the sensor answers
with an Acknowledge Bit (logical 0) on the output.
–
Read a register (see
Fig. 5
–
3
)
After evaluating this command the sensor answers
with the Acknowledge Bit, 14 Data Bits, and the
Data Parity Bit on the output.
–
Programming the EEPROM cells (see
Fig. 5
–
4
)
After evaluating this command the sensor answers
with the Acknowledge Bit. After the delay time t
w
the
supply voltage rises up to the programming voltage.
Fig. 5
–
1:
Definition of logical 0 and 1 bit
t
r
t
f
t
p0
t
p0
logical 0
V
DDH
V
DDL
or
t
p0
logical 1
V
DDH
V
DDL
or
t
p0
t
p1
t
p1
Table 5
–
1:
Telegram parameters
Symbol
Parameter
Pin
Min.
Typ.
Max.
Unit
Remarks
V
DDL
Supply Voltage for Low Level
during Programming
1
5
5.6
6
V
V
DDH
Supply Voltage for High Level
during Programming
1
6.8
8.0
8.5
V
t
r
Rise time
1
0.05
ms
t
f
Fall time
1
0.05
ms
t
p0
Bit time on V
DD
1
3.4
3.5
3.6
ms
t
p0
is defined through the Sync Bit
t
pOUT
Bit time on output pin
3
4
6
8
ms
t
is defined through the
Acknowledge Bit
t
p1
Voltage Change for logical 1
1, 3
50
65
80
%
% of t
p0
or t
pOUT
V
DDPROG
Supply Voltage for
Programming the EEPROM
1
11.95
12
12.1
V
t
PROG
Programming Time for EEPROM
1
95
100
105
ms
t
rp
Rise time of programming voltage
1
0.2
0.5
1
ms
t
fp
Fall time of programming voltage
1
0
1
ms
t
w
Delay time of programming voltage
after Acknowledge
1
0.5
0.7
1
ms
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