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參數(shù)資料
| 型號(hào)： | GTLP6C817MTCX |
| 英文描述： | Eight Distributed-Output Clock Driver |
| 中文描述： | 八分布式輸出時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 64K |
| 代理商： | GTLP6C817MTCX |
2000 Fairchild Semiconductor Corporation
DS500179
www.fairchildsemi.com
August 1998
Revised December 2000
G
GTLP6C816A
GTLP/LVTTL 1:6 Clock Driver
General Description
The GTLP6C816A is a clock driver that provides LVTTL to
GTLP signal level translation (and vice versa). The device
provides a high speed interface between cards operating at
LVTTL logic levels and a backplane operating at GTL(P)
logic levels. High speed backplane operation is a direct
result of GTLP’s reduced output swing (
<
1V), reduced input
threshold levels and output edge rate control. The edge
rate control minimizes bus settling time. GTLP is a Fairchild
Semiconductor derivative of the Gunning Transceiver logic
(GTL) JEDEC standard JESD8-3.
Fairchild’s GTL(P) has internal edge-rate control and is
process, voltage, and temperature (PVT) compensated. Its
function is similar to BTL and GTL but with different output
levels and receiver threshold. GTLP output LOW level is
typically less than 0.5V, the output level HIGH is 1.5V and
the receiver threshold is 1.0V.
Features
I
Interface between LVTTL and GTLP logic levels
I
Designed with edge rate control circuitry to reduce out-
put noise on the GTLP port
I
V
REF
pin provides external supply reference voltage for
receiver threshold adjustibility
I
Special PVT compensation circuitry to provide consis-
tent performance over variations of process, supply volt-
age and temperature
I
TTL compatible driver and control inputs
I
Designed using Fairchild advanced BiCMOS technology
I
Bushold data inputs on A port to eliminate the need for
external pull-up resistors for unused inputs
I
Power up/down and power off high impedance for live
insertion
I
Open drain on GTLP to support wired-or connection
I
A Port source/sink
24mA/
+
24mA
I
B Port sink
+
50mA
I
1:6 fanout clock driver for TTL port
I
1:2 fanout clock driver for GTLP port
I
Low voltage version of GTLP6C816
Ordering Code:
Device is also available in Tape and Reel. Specify by appending the suffix letter
“
X
”
to the ordering code.
Pin Descriptions
Connection Diagram
Order Number
GTLP6C816AMTC
Package Number
MTC24
Package Description
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names
Description
TTLIN, GTLPIN Clock Inputs
(LVTTL and GTLP respectively)
OEB
Output Enable (Active LOW)
GTLP Port (LVTTL Levels)
OEA
Output Enable (Active LOW)
TTL Port (LVTTL Levels)
V
CCT
.GNDT
V
CC
GNDG
TTL Output Supplies
Internal Circuitry V
CC
OBn GTLP Output Grounds
V
REF
OA0
–
OA5
Voltage Reference Input
TTL Buffered Clock Outputs
OB0
–
OB1
GTLP Buffered Clock Outputs
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GTLP6C816 | GTLP-to-TTL 1:6 Clock Driver |
| GTLP6C816MTC | GTLP-to-TTL 1:6 Clock Driver |
| GTLP6C817 | Low Drive GTLP-to-LVTTL 1:6 Clock Driver |
| GTLP6C817MTC | Low Drive GTLP-to-LVTTL 1:6 Clock Driver |
| GTLP8T306MTCX | Single 8-bit Bus Transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GTLP75X1800 | 制造商:HellermannTyton 功能描述:Low profile Grip Tie roll - .5 wide - Black |
| GTLP8T306 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:8-Bit LVTTL/GTLP Bus Transceiver |
| GTLP8T306MTC | 功能描述:總線收發(fā)器 8-Bit Bus Trans RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| GTLP8T306MTCX | 功能描述:總線收發(fā)器 8-Bit Bus Trans RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| GTLPBT306MTCX | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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