參數(shù)資料
型號： GS9062*
英文描述： 270Mb/s Serializer with EDH for SDI and DVB-ASI. 3.3/1.8V supply.
中文描述： 270Mb / s的空間數(shù)據(jù)基礎(chǔ)設(shè)施和DVB硬腦膜外血腫序列化，意大利航天局。 3.3/1.8V供應(yīng)。
文件頁數(shù)： 3/47頁
文件大?。?/td> 754K
GENNUM CORPORATION
22208 - 0
3 of 47
G
TABLE OF CONTENTS
1. PIN OUT ..........................................................................................................................................5
1.1 PIN ASSIGNMENT................................................................................................................5
1.2 PIN DESCRIPTIONS..............................................................................................................6
2. ELECTRICAL CHARACTERISTICS ........................................................................................................13
2.1 ABSOLUTE MAXIUMUM RATINGS........................................................................................13
2.2 DC ELECTRICAL CHARACTERISTICS......................................................................................14
2.3 AC ELECTRICAL CHARACTERISTICS......................................................................................15
2.4 INPUT/OUTPUT CIRCUITS ..................................................................................................17
2.5 HOST INTERFACE MAP.......................................................................................................18
3. DETAILED DESCRIPTION...................................................................................................................21
3.1 FUNCTIONAL OVERVIEW ....................................................................................................21
3.2 SERIAL DIGITAL INPUT .......................................................................................................21
3.2.1 INPUT SIGNAL SELECTION ................................................................................................................................21
3.2.2 CARRIER DETECT INPUT....................................................................................................................................21
3.2.3 SINGLE INPUT CONFIGURATION ......................................................................................................................21
3.3 SERIAL DIGITAL RECLOCKER ...............................................................................................21
3.3.1 EXTERNAL VCO...................................................................................................................................................22
3.3.2 LOOP BANDWIDTH.............................................................................................................................................22
3.4 SERIAL DIGITAL LOOP-THROUGH OUTPUT.............................................................................22
3.4.1 OUTPUT SWING..................................................................................................................................................22
3.4.2 RECLOCKER BYPASS CONTROL.......................................................................................................................22
3.4.3 SERIAL DIGITAL OUTPUT MUTE ........................................................................................................................22
3.5 SERIAL-TO-PARALLEL CONVERSION......................................................................................23
3.6 LOCK DETECT ...................................................................................................................23
3.6.1 INPUT CONTROL SIGNALS ................................................................................................................................23
3.7 SMPTE FUNCTIONALITY .....................................................................................................24
3.7.1 SMPTE DESCRAMBLING AND WORD ALIGNMENT ..........................................................................................24
3.7.2 INTERNAL FLYWHEEL.........................................................................................................................................24
3.7.3 SWITCH LINE LOCK HANDLING ........................................................................................................................24
3.7.4 HVF TIMING SIGNAL GENERATION...................................................................................................................27
3.8 DVB-ASI FUNCTIONALITY....................................................................................................28
3.8.1 DVB-ASI 8B/10B DECODING AND WORD ALIGNMENT....................................................................................28
3.8.2 STATUS SIGNAL OUTPUTS ................................................................................................................................28
3.9 DATA THROUGH MODE......................................................................................................28
3.10 ADDITIONAL PROCESSING FUNCTIONS...............................................................................28
3.10.1 FIFO LOAD PULSE ............................................................................................................................................28
3.10.2 ANCILLARY DATA DETECTION AND INDICATION..........................................................................................29
3.10.3 SMPTE 352M PAYLOAD IDENTIFIER................................................................................................................31
3.10.4 AUTOMATIC VIDEO STANDARD AND DATA FORMAT DETECTION...............................................................31
3.10.5 ERROR DETECTION AND INDICATION............................................................................................................33
3.10.6 ERROR CORRECTION AND INSERTION ..........................................................................................................37
3.10.7 EDH FLAG DETECTION.....................................................................................................................................38
3.11 PARALLEL DATA OUTPUTS...............................................................................................39
3.11.1 PARALLEL DATA BUS BUFFERS ......................................................................................................................39
3.11.2 PARALLEL OUTPUT IN SMPTE MODE..............................................................................................................40
3.11.3 PARALLEL OUTPUT IN DVB-ASI MODE ...........................................................................................................40
3.11.4 PARALLEL OUTPUT IN DATA-THROUGH MODE.............................................................................................40
3.11.5 PARALLEL OUTPUT CLOCK (PCLK) ................................................................................................................40
3.12 GSPI HOST INTERFACE.....................................................................................................41
3.12.1 COMMAND WORD DESCRIPTION....................................................................................................................41
3.12.2 DATA READ AND WRITE TIMING .....................................................................................................................42
3.12.3 CONFIGURATION AND STATUS REGISTERS ..................................................................................................42
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