- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370391 > GS9062* 270Mb/s Serializer with EDH for SDI and DVB-ASI. 3.3/1.8V supply. PDF資料下載
參數(shù)資料
| 型號(hào)： | GS9062* |
| 英文描述： | 270Mb/s Serializer with EDH for SDI and DVB-ASI. 3.3/1.8V supply. |
| 中文描述： | 270Mb / s的空間數(shù)據(jù)基礎(chǔ)設(shè)施和DVB硬腦膜外血腫序列化，意大利航天局。 3.3/1.8V供應(yīng)。 |
| 文件頁數(shù)： | 12/47頁 |
| 文件大小： | 754K |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當(dāng)前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁
GENNUM CORPORATION
22208 - 0
12 of 47
G
69
PCLK
-
Output
PARALLEL DATA BUS CLOCK
Signal levels are LVCMOS/LVTTL compatible.
20-bit mode
PCLK = 13.5MHz
10-bit mode
PCLK = 27MHz
70
RC_BYP
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
When set HIGH, the serial digital output will be a reclocked version of the
input signal regardless of whether the device is in SMPTE, DVB-ASI or
Data-Through mode.
When set LOW, the serial digital output will be a buffered version of the
input signal in all modes.
71
NC
-
-
No connect.
72
LOCKED
Synchronous
with PCLK
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS / LVTTL compatible.
The LOCKED signal will be HIGH whenever the device has correctly
received and locked to SMPTE compliant data in SMPTE mode or DVB-
ASI compliant data in DVB-ASI mode, or when the reclocker has achieved
lock in Data-Through mode.
It will be LOW otherwise.
73, 74
VCO, VCO
Analog
Input
Differential inputs for the external VCO reference signal. For single ended
devices such as the GO1525, VCO should be AC coupled to VCO_GND.
75
VCO_GND
-
Output
Power
Ground reference for the external voltage controlled oscillator. Connect to
pins 2, 4, 6, and 8 of the GO1525. This pin is an output.
Should be isolated from all other grounds.
76
VCO_VCC
-
Output
Power
Power supply for the external voltage controlled oscillator. Connect to pin
5 of the GO1525. This pin is an output.
Should be isolated from all other power supplies.
77
LF
Analog
Output
Control voltage to external voltage controlled oscillator. Nominally +1.25V
DC.
78
CP_CAP
Analog
Input
PLL lock time constant capacitor connection. Normally connected to
VCO_GND through 2.2nF.
79
LB_CONT
Analog
Input
Control voltage to set the loop bandwidth of the integrated reclocker.
Normally connected to VCO_GND through 40k
.
80
CP_GND
-
Power
Ground connection for the charge pump. Connect to analog GND.
1.2 PIN DESCRIPTIONS (CONTINUED)
PIN
NUMBER
NAME
TIMING
TYPE
DESCRIPTION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS9064 | Telecomm/Datacomm |
| GSA1 | Fuse |
| GSA1.25 | Fuse |
| GSA1.6 | Fuse |
| GSA10 | Fuse |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS9062_07 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD-LINX II SD-SDI and DVB-ASI Serializer with ClockCleaner |
| GS9062-CF | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD-LINX II SD-SDI and DVB-ASI Serializer with ClockCleaner |
| GS9062-CFE3 | 制造商:Semtech Corporation 功能描述:Dual Standard Serializer 80-Pin LQFP 制造商:Semtech Corporation 功能描述:Transmitter for SD-SDI & DVB-ASI |
| GS9064 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。