參數(shù)資料
型號: GS88136CT-250V
廠商: GSI TECHNOLOGY
元件分類: SRAM
英文描述: CACHE SRAM, PQFP100
封裝: TQFP-100
文件頁數(shù): 22/36頁
文件大?。?/td> 1540K
代理商: GS88136CT-250V
GS88118/32/36C(T/D)-xxxV
Rev: 1.00 9/2008
29/36
2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
JTAG Port Recommended Operating Conditions and DC Characteristics (1.8/2.5 V Version)
Parameter
Symbol
Min.
Max.
Unit Notes
1.8 V Test Port Input Low Voltage
VILJ1
0.3
0.3 * VDD1
V
1
2.5 V Test Port Input Low Voltage
VILJ2
0.3
0.3 * VDD2
V
1
1.8 V Test Port Input High Voltage
VIHJ1
0.6 * VDD1
VDD1 +0.3
V
1
2.5 V Test Port Input High Voltage
VIHJ2
0.6 * VDD2
VDD2 +0.3
V
1
TMS, TCK and TDI Input Leakage Current
IINHJ
300
1
uA
2
TMS, TCK and TDI Input Leakage Current
IINLJ
1
100
uA
3
TDO Output Leakage Current
IOLJ
1
uA
4
Test Port Output High Voltage
VOHJ
1.7
V
5, 6
Test Port Output Low Voltage
VOLJ
0.4
V
5, 7
Test Port Output CMOS High
VOHJC
VDDQ – 100 mV
V
5, 8
Test Port Output CMOS Low
VOLJC
100 mV
V
5, 9
Notes:
1. Input Under/overshoot voltage must be –2 V < Vi < VDDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.
2. VILJ ≤ VIN ≤ VDDn
3. 0 V
≤ V
IN ≤ V
ILJn
4. Output Disable, VOUT = 0 to VDDn
5. The TDO output driver is served by the VDDQ supply.
6. IOHJ = –4 mA
7. IOLJ = + 4 mA
8. IOHJC = –100 uA
9. IOLJC = +100 uA
Notes:
1. Include scope and jig capacitance.
2. Test conditions as shown unless otherwise noted.
JTAG Port AC Test Conditions
Parameter
Conditions
Input high level
VDD – 0.2 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
VDDQ/2
Output reference level
VDDQ/2
DQ
VDDQ/2
50
Ω
30pF*
JTAG Port AC Test Load
* Distributed Test Jig Capacitance
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