參數(shù)資料
型號(hào)： GS88136CT-250V
廠商： GSI TECHNOLOGY
元件分類(lèi)： SRAM
英文描述： CACHE SRAM, PQFP100
封裝： TQFP-100
文件頁(yè)數(shù)： 18/36頁(yè)
文件大?。?/td> 1540K
代理商： GS88136CT-250V
GS88118/32/36C(T/D)-xxxV
Rev: 1.00 9/2008
25/36
2008, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
JTAG TAP Block Diagram
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
Not Used
GSI Technology
JEDEC Vendor
ID Code
Presence
Register
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
X X X X X X X X X X X X X X X X X X X X 0
0 0 1 1 0 1 1 0 0 1
1
Instruction Register
ID Code Register
Boundary Scan Register
0
1
2
0
31 30 29
1
2
0
Bypass Register
TDI
TDO
TMS
TCK
Test Access Port (TAP) Controller
M*
1
0
Control Signals
* For the value of M, see the BSDL file, which is available at by contacting us at apps@gsitechnology.com.
相關(guān)PDF資料
PDF描述
GS881E18AD-133 512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
GS881E18AD-133I 512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
GS881E18AD-133IT 512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
GS881E18AD-133T 512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
GS881E18AD-150 512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
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