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參數(shù)資料
| 型號(hào)： | GS880Z18 |
| 廠商： | GSI TECHNOLOGY |
| 英文描述： | 8Mb Pipelined and Flow Through Synchronous NBT SRAM(8M位流水線式和流通型同步NBT靜態(tài)RAM) |
| 中文描述： | 8MB的流水線和流量，通過同步唑的SRAM（800萬位流水線式和流通型同步唑靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 12/25頁 |
| 文件大?。?/td> | 404K |
| 代理商： | GS880Z18 |
Rev: 1.10 8/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
12/25
1998, Giga Semconductor, Inc.
Preliminary
.
GS880Z18/36T-11/100/80/66
Sleep Mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I
SB
2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
Designing for Compatibility
The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal found
on Pin 14. Not all vendors offer this option, however, most mark Pin 14 as V
DD
or V
DDQ
on pipelined parts and V
SS
on flow
through parts. GSI NBT SRAMs are fully compatible with these sockets.
Pin 66, a No Connect (NC) on GSI’s GS880Z18/36 NBT SRAM, the Parity Error open drain output on GSI’s GS881Z18/36 NBT
SRAM, is often marked as a power pin on other vendor’s NBT-compatible SRAMs. Specifically, it is marked V
DD
or V
DDQ
on
pipelined parts and V
SS
on flow through parts. Users of GSI NBT devices who are not actually using the ByteSafe parity feature
may want to design the board site for the RAM with Pin 66 tied high through a 1k ohm resistor in Pipeline mode applications or
tied low in Flow Through mode applications in order to keep the option to use non-configurable devices open. By using the pull-up
resistor, rather than tying the pin to one of the power rails, users interested in upgrading to GSI’s ByteSafe NBT SRAMs
(GS881Z18/36), featuring Parity Error detection and JTAG Boundary Scan, will be ready for connection to the active low, open
drain Parity Error output driver at Pin 66 on GSI’s TQFP ByteSafe RAMs.
CK
ZZ
tZZR
tZZH
tZZS
~
~
Sleep
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