參數(shù)資料
型號(hào)： GS880F18T-14T
廠(chǎng)商： GSI TECHNOLOGY
元件分類(lèi)： SRAM
英文描述： 512K X 18 CACHE SRAM, 14 ns, PQFP100
封裝： TQFP-100
文件頁(yè)數(shù)： 19/22頁(yè)
文件大?。?/td> 310K
代理商： GS880F18T-14T
Rev: 1.06 9/2000
6/22
2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880F18/36T-11/11.5/12/14/18
Note:
There is a pull-up device on the LBO pin and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will operate
in the default states as specified in the above table.
Burst Counter Sequences
BPR 1999.05.18
Byte Write Truth Table
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the and x36 version.
Mode Pin Functions
Mode Name
Pin Name
State
Function
Burst Order Control
LBO
L
Linear Burst
H or NC
Interleaved Burst
Power Down Control
ZZ
L or NC
Active
H
Standby, IDD = ISB
Function
GW
BW
BA
BB
BC
BD
Notes
Read
H
X
1
Read
H
L
H
1
Write byte a
H
L
H
2, 3
Write byte b
H
L
H
L
H
2, 3
Write byte c
H
L
H
L
H
2, 3, 4
Write byte d
H
L
H
L
2, 3, 4
Write all bytes
H
L
2, 3, 4
Write all bytes
L
X
Linear Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
Interleaved Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
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