參數(shù)資料
型號(hào): GS840E18AT-166IT
廠(chǎng)商: GSI TECHNOLOGY
元件分類(lèi): SRAM
英文描述: 256K X 18 CACHE SRAM, 8.5 ns, PQFP100
封裝: TQFP-100
文件頁(yè)數(shù): 32/32頁(yè)
文件大?。?/td> 950K
代理商: GS840E18AT-166IT
GS840E18/32/36AT/B-180/166/150/100
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.14 10/2007
9/32
1999, GSI Technology
BGA Pin Description
Symbol
Type
Description
A0, A1
I
Address field LSBs and Address Counter Preset Inputs
A
I
Address Inputs
BA
In
Byte Write signal for data inputs DQA; active low
BB
In
Byte Write signal for data inputs DQB; active low
BC
In
Byte Write signal for data inputs DQC; active low
BD
In
Byte Write signal for data inputs DQD; active low
CK
I
Clock Input Signal; active high
BW
I
Byte Write—Writes all enabled bytes; active low
GW
I
Global Write Enable—Writes all bytes; active low
E1, E3
I
Chip Enable; active low
E2
I
Chip Enable; active high
G
I
Output Enable; active low
ADV
I
Burst address counter advance enable; active low
ADSP, ADSC
I
Address Strobe (Processor, Cache Controller); active low
DQA
I/O
Byte A Data Input and Output pins
DQB
I/O
Byte B Data Input and Output pins
DQ
I/O
Byte C Data Input and Output pins
DQD
I/O
Byte D Data Input and Output pins
DQPA
I/O
9th Data I/O Pin; Byte A
DQPB
I/O
9th Data I/O Pin; Byte B
DQPC
I/O
9th Data I/O Pin; Byte C
DQPD
I/O
9th Data I/O Pin; Byte D
ZZ
I
Sleep Mode control; active high
FT
I
Flow Through or Pipeline mode; active low
LBO
I
Linear Burst Order mode; active low
VDD
I
Core power supply
VSS
I
I/O and Core Ground
VDDQ
I
Output driver power supply
NC
No Connect
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