參數(shù)資料
型號(hào): GS820H32GT-138I
廠商: GSI TECHNOLOGY
元件分類: SRAM
英文描述: 64K X 32 CACHE SRAM, 9.7 ns, PQFP100
封裝: TQFP-100
文件頁(yè)數(shù): 21/23頁(yè)
文件大?。?/td> 342K
代理商: GS820H32GT-138I
Rev: 1.03 2/2000
7/23
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
D
GS820H32T/Q-150/138/133/117/100/66
First Write
First Read
Burst Write
Burst Read
Deselect
R
W
CR
CW
X
W
R
W
R
X
Si
m
pl
e
Sy
nc
hr
on
ou
s
O
pe
ra
tio
n
Si
m
pl
e
Bu
rs
tS
yn
ch
ro
no
us
O
pe
ra
tio
n
CR
R
CW
CR
Simplified State Diagram
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied Low.
2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, E3) and Write (BA, BB, BC, BD, BW and GW) control inputs
and that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write and ADSC control inputs and assumes
ADSP is tied high and ADV is tied low.
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