參數(shù)資料
型號(hào)： GS820H32GT-138I
廠商： GSI TECHNOLOGY
元件分類(lèi)： SRAM
英文描述： 64K X 32 CACHE SRAM, 9.7 ns, PQFP100
封裝： TQFP-100
文件頁(yè)數(shù)： 17/23頁(yè)
文件大?。?/td> 342K
代理商： GS820H32GT-138I
Rev: 1.03 2/2000
3/23
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
D
GS820H32T/Q-150/138/133/117/100/66
TQFP Pin Description
H
Pin Location
Symbol
Type
Description
37, 36
A0, A1
I
Address field LSB’s and Address Counter preset Inputs
35, 34, 33, 32, 100, 99, 82, 81, 44, 45,
46, 47, 48, 49
A2-15
I
Address Inputs
52, 53, 56, 57, 58, 59, 62, 63
68, 69, 72, 73, 74, 75, 78, 79
2, 3, 6, 7, 8, 9, 12, 13
18, 19, 22, 23, 24, 25, 28, 29
DQA1-DQA8
DQB1-DQB8
DQC1-DQC8
DQD1-DQD8
I/O
Data Input and Output pins.
16, 38, 39, 42, 43, 66, 50, 51, 80, 1, 30
NC
No Connect
87
BW
I
Byte Write. Writes all enabled bytes. Active Low.
93, 94
BA, BB
I
Byte Write Enable for DQA, DQB Data I/O’s. Active Low.
95, 96
BC, BD
I
Byte Write Enable for DQC, DQD Data I/O’s. Active Low.
89
CK
I
Clock Input Signal. Active High.
88
GW
I
Global Write Enable. Writes all bytes. Active Low.
98, 92
E1, E3
I
Chip Enable. Active Low.
97
E2
I
Chip Enable. Active High.
86
G
I
Output Enable. Active Low.
83
ADV
I
Burst address counter advance enable. Active Low.
84, 85
ADSP, ADSC
I
Address Strobe (Processor, Cache Controller). Active Low.
64
ZZ
I
Sleep Mode control. Active High.
14
FT
I
Flow Through or Pipeline mode. Active Low.
31
LBO
I
Linear Burst Order mode. Active Low.
15, 41, 65, 91
VDD
I
Core power supply.
5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90
VSS
I
I/O and Core Ground.
4, 11, 20, 27, 54, 61, 70, 77
VDDQ
I
Output driver power supply.
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