參數(shù)資料
型號(hào)： GS8170S18
廠商： GSI TECHNOLOGY
英文描述： 16Mb（1M x 18Bit）Synchronous SRAM(16M位（1M x 18位）同步靜態(tài)RAM)
中文描述： 16Mb的（100萬x 18位）同步SRAM（1,600位（100萬× 18位）同步靜態(tài)內(nèi)存）
文件頁數(shù)： 33/38頁
文件大?。?/td> 934K
代理商： GS8170S18
Rev: 1.01 11/2000
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
33/38
2000, Giga Semiconductor, Inc.
A
Advanced Information
GS8170S18/36/72B-333/300/275/250
JTAG TAP Instruction Set Summary
JTAG Port Recommended Operating Conditions and DC Characteristics
Instruction
Code
Description
Notes
EXTEST-A
000
Places the Boundary Scan Register between TDI and TDO.
This RAM implements an Clock Assisted EXTEST function. *Not 1149.1 Compliant *
Preloads ID Register and places it between TDI and TDO.
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
Forces all Data and Clock output drivers to High-Z.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
This RAM does not implement 1149.1 PRELOAD function. *Not 1149.1 Compliant *
GSI Private instruction.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
Places Bypass Register between TDI and TDO.
1
IDCODE
001
1, 2
SAMPLE-Z
010
1
RFU
011
1
SAMPLE/
PRELOAD
GSI
100
1
101
1
RFU
110
1
BYPASS
Notes:
1.
Instruction codes expressed in binary, MSB on left, LSB on right.
2.
Default instruction automatically loaded at power-up and in Test-Logic-Reset state.
111
1
Parameter
Symbol
V
IHT
V
ILT
I
INTH
I
INTL
I
OLT
V
OHT
V
OLT
Min.
0.65 * V
DD
Max.
V
DD
+0.3
0.35 * V
DD
Unit
Notes
Test Port Input High Voltage
V
1
Test Port Input Low Voltage
–0.3
V
1
TMS, TCK and TDI Input Leakage Current
–100
2
uA
2
TMS, TCK and TDI Input Leakage Current
–2
2
uA
3
TDO Output Leakage Current
–2
2
uA
4
Test Port Output High Voltage
V
DDQ
– 100 mV
—
V
5, 6
Test Port Output Low Voltage
—
100 mV
V
7
Notes:
1.
2.
3.
4.
5.
6.
7.
Input Under/overshoot voltage must be –1 V < Vi < V
DD
+ 1 V with a pulse width not to exceed 20% tTKC.
V
DD
≥
V
IN
≥
V
IL
0 V
≤
V
IN
≤
V
IL
Output Disable, V
OUT
= 0 to V
DD
The TDO output driver is served by the V
DD
supply.
I
OH
= –100 uA
I
OL
= +100 uA
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